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  1.  
  2. BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
  3.  
  4. Board ID = 8
  5. Set A53 clk to 24M
  6. Set A73 clk to 24M
  7. Set clk81 to 24M
  8. A53 clk: 1200 MHz
  9. A73 clk: 1200 MHz
  10. CLK81: 166.6M
  11. smccc: 000347c4
  12. eMMC boot @ 0
  13. sw8 s
  14. DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
  15. board id: 8
  16. Load FIP HDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
  17. fw parse done
  18. Load ddrfw from eMMC, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0
  19. Load ddrfw from eMMC, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0
  20. PIEI prepare done
  21. fastboot data load
  22. 00000000
  23. emmc switch 1 ok
  24. 00000000
  25. emmc switch 2 ok
  26. fastboot data verify
  27. verify result: 265
  28. Cfg max: 4, cur: 1. Board id: 255. Force loop cfg
  29. LPDDR4 probe
  30. ddr clk to 1608MHz
  31. Load ddrfw from eMMC, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0
  32. 00000000
  33. emmc switch 0 ok
  34.  
  35. dmc_version 0001
  36. Check phy result
  37. INFO : End of CA training
  38. INFO : End of initialization
  39. INFO : Training has run successfully!
  40. Check phy result
  41. INFO : End of initialization
  42. INFO : End of read enable training
  43. INFO : End of fine write leveling
  44. INFO : End of Write leveling coarse delay
  45. INFO : Training has run successfully!
  46. Check phy result
  47. INFO : End of initialization
  48. INFO : End of read dq deskew training
  49. INFO : End of MPR read delay center optimization
  50. INFO : End of write delay center optimization
  51. INFO : End of read delay center optimization
  52. INFO : End of max read latency training
  53. INFO : Training has run successfully!
  54. 1D training succeed
  55. Load ddrfw from eMMC, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0
  56. Check phy result
  57. INFO : End of initialization
  58. INFO : End of 2D read delay Voltage center optimization
  59. INFO : End of 2D read delay Voltage center optimization
  60. INFO : End of 2D write delay Voltage center optimization
  61. INFO : End of 2D write delay Voltage center optimization
  62. INFO : Training has run successfully!
  63.  
  64. channel==0
  65. RxClkDly_Margin_A0==87 ps 9
  66. TxDqDly_Margin_A0==106 ps 11
  67. RxClkDly_Margin_A1==97 ps 10
  68. TxDqDly_Margin_A1==106 ps 11
  69. TrainedVREFDQ_A0==26
  70. TrainedVREFDQ_A1==26
  71. VrefDac_Margin_A0==26
  72. DeviceVref_Margin_A0==26
  73. VrefDac_Margin_A1==28
  74. DeviceVref_Margin_A1==26
  75.  
  76.  
  77. channel==1
  78. RxClkDly_Margin_A0==97 ps 10
  79. TxDqDly_Margin_A0==97 ps 10
  80. RxClkDly_Margin_A1==97 ps 10
  81. TxDqDly_Margin_A1==106 ps 11
  82. TrainedVREFDQ_A0==25
  83. TrainedVREFDQ_A1==24
  84. VrefDac_Margin_A0==28
  85. DeviceVref_Margin_A0==24
  86. VrefDac_Margin_A1==29
  87. DeviceVref_Margin_A1==24
  88.  
  89. dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  90.  
  91. soc_vref_reg_value 0x 00000026 00000028 00000028 00000028 00000027 00000027 00000027 002
  92. 2D training succeed
  93. aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
  94. auto size-- 65535DDR cs0 size: 2048MB
  95. DDR cs1 size: 2048MB
  96. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  97. cs0 DataBus test pass
  98. cs1 DataBus test pass
  99. cs0 AddrBus test pass
  100. cs1 AddrBus test pass
  101.  
  102. 100bdlr_step_size ps== 409
  103. result report
  104. boot times 0Enable ddr reg access
  105. 00000000
  106. emmc switch 3 ok
  107. Authentication key not yet programmed
  108. get rpmb counter error 0x00000007
  109. 00000000
  110. emmc switch 0 ok
  111. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  112. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x000dc000, part: 0
  113. 0.0;M3 CHK:0;cm4_sp_mode 0
  114. MVN_1=0x00000000
  115. MVN_2=0x00000000
  116. [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
  117. OPS=0x10
  118. ring efuse init
  119. chipver efuse init
  120. 29 0b 10 00 01 10 20 00 00 01 37 30 4e 42 4e 50
  121. [0.018961 Inits done]
  122. secure task start!
  123. high task start!
  124. low task start!
  125. run into bl31
  126. NOTICE: BL31: v1.3(release):4fc40b1
  127. NOTICE: BL31: Built : 15:58:17, May 22 2019
  128. NOTICE: BL31: G12A normal boot!
  129. NOTICE: BL31: BL33 decompress pass
  130. ERROR: Error initializing runtime service opteed_fast
  131.  
  132.  
  133. U-Boot 2015.01-g4752efb (Mar 19 2020 - 11:49:51)
  134.  
  135. DRAM: 3.8 GiB
  136. Relocation Offset is: d6e22000
  137. spi_post_bind(spifc): req_seq = 0
  138. register usb cfg[0][1] = 00000000d7f28538
  139. aml_i2c_init_port init regs for 0
  140. NAND: get_sys_clk_rate_mtd() 290, clock setting 200!
  141. NAND device id: 0 9f ff ff ff ff
  142. No NAND device found!!!
  143. nand init failed: -6
  144. get_sys_clk_rate_mtd() 290, clock setting 200!
  145. NAND device id: 0 9f ff ff ff ff
  146. No NAND device found!!!
  147. nand init failed: -6
  148. MMC: aml_priv->desc_buf = 0x00000000d3e12a70
  149. aml_priv->desc_buf = 0x00000000d3e14db0
  150. SDIO Port B: 0, SDIO Port C: 1
  151. co-phase 0x3, tx-dly 0, clock 400000
  152. co-phase 0x3, tx-dly 0, clock 400000
  153. co-phase 0x3, tx-dly 0, clock 400000
  154. emmc/sd response timeout, cmd8, status=0x3ff2800
  155. emmc/sd response timeout, cmd55, status=0x3ff2800
  156. co-phase 0x3, tx-dly 0, clock 400000
  157. co-phase 0x1, tx-dly 0, clock 40000000
  158. aml_sd_retry_refix[983]:delay = 0x0,gadjust =0x2000
  159. [mmc_startup] mmc refix success
  160. init_part() 297: PART_TYPE_AML
  161. [mmc_init] mmc init success
  162. start dts,buffer=00000000d3e17620,dt_addr=00000000d3e17620
  163. get_partition_from_dts() 91: ret 0
  164. parts: 17
  165. 00: logo 0000000000800000 1
  166. 01: recovery 0000000001800000 1
  167. 02: misc 0000000000800000 1
  168. 03: dtbo 0000000000800000 1
  169. 04: cri_data 0000000000800000 2
  170. 05: param 0000000001000000 2
  171. 06: boot 0000000001000000 1
  172. set has_boot_slot = 0
  173. 07: rsv 0000000001000000 1
  174. 08: metadata 0000000001000000 1
  175. 09: vbmeta 0000000000200000 1
  176. 10: tee 0000000002000000 1
  177. 11: vendor 0000000014000000 1
  178. 12: odm 0000000008000000 1
  179. 13: system 0000000050000000 1
  180. 14: product 0000000008000000 1
  181. 15: cache 0000000046000000 2
  182. 16: data ffffffffffffffff 4
  183. init_part() 297: PART_TYPE_AML
  184. eMMC/TSD partition table have been checked OK!
  185. crc32_s:0x1577dad == storage crc_pattern:0x1577dad!!!
  186. crc32_s:0xee152b83 == storage crc_pattern:0xee152b83!!!
  187. crc32_s:0x79f50f07 == storage crc_pattern:0x79f50f07!!!
  188. mmc env offset: 0x4d400000
  189. In: serial
  190. Out: serial
  191. Err: serial
  192. reboot_mode=cold_boot
  193. [store]To run cmd[emmc dtb_read 0x1000000 0x40000]
  194. _verify_dtb_checksum()-3477: calc 58267ef1, store 0
  195. update_dtb_info()-3585: cpy 1 is not valid
  196. _verify_dtb_checksum()-3477: calc 58267ef1, store 0
  197. update_dtb_info()-3585: cpy 0 is not valid
  198. dtb_read()-3694: total valid 0
  199. emmc - EMMC sub system
  200.  
  201. Usage:
  202. emmc dtb_read addr size
  203. emmc dtb_write addr size
  204. emmc erase dtb
  205. emmc erase key
  206. emmc fastboot_read addr size
  207. emmc fastboot_write addr size
  208.  
  209. aml_i2c_init_port init regs for 0
  210. fusb302_init: Device ID: 0x91
  211. CC connected in 0 as UFP
  212. fusb302 detect chip.port_num = 0
  213. amlkey_init() enter!
  214. [EFUSE_MSG]keynum is 1
  215. vpu: clk_level in dts: 7
  216. vpu: vpu_power_on
  217. vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100)
  218. vpu: vpu_module_init_config
  219. vpp: vpp_init
  220. vpp: vpp osd2 matrix rgb2yuv..............
  221. cvbs: cpuid:0x29
  222. LCD_RESET PIN: 0
  223. lcd: detect mode: tablet, key_valid: 0
  224. lcd: detect lcd_clk_path: 1
  225. lcd: failed to get lcd_cpu_gpio_names
  226. lcd: load config from dts
  227. lcd: pinctrl_version: 2
  228. lcd: use panel_type=lcd_1
  229. lcd: bl: pinctrl_version: 2
  230. lcd: bl: name: backlight_pwm, method: 1
  231. lcd: bl: pwm_reg=0x00800002
  232. lcd: error: gpio: wrong name invalid
  233. lcd: bl: aml_bl_power_ctrl: 0
  234. Net: dwmac.ff3f0000amlkey_init() enter!
  235. amlkey_init() 71: already init!
  236. [EFUSE_MSG]keynum is 1
  237. MACADDR:02:00:00:20:10:01(from chipid)
  238.  
  239. CONFIG_AVB2: null
  240. Start read misc partition datas!
  241. info->magic =
  242. info->version_major = 1
  243. info->version_minor = 0
  244. info->slots[0].priority = 15
  245. info->slots[0].tries_remaining = 7
  246. info->slots[0].successful_boot = 0
  247. info->slots[1].priority = 14
  248. info->slots[1].tries_remaining = 7
  249. info->slots[1].successful_boot = 0
  250. info->crc32 = -1075449479
  251. active slot = 0
  252.  
  253. wipe_data=successful
  254. wipe_cache=successful
  255. upgrade_step=2
  256. reboot_mode:::: cold_boot
  257.  
  258.  
  259. lcd: error: outputmode[1080p60hz] is not support
  260. hpd_state=0
  261. edid preferred_mode is <NULL>[0]
  262. hdr mode is 0
  263. dv mode is ver:0 len: 0
  264. hdr10+ mode is 0
  265. [OSD]load fb addr from dts:/meson-fb
  266. [OSD]set initrd_high: 0x7f800000
  267. [OSD]fb_addr for logo: 0x7f800000
  268. [OSD]load fb addr from dts:/meson-fb
  269. [OSD]fb_addr for logo: 0x7f800000
  270. [CANVAS]canvas init
  271. [CANVAS]addr=0x7fbf4800 width=2176, height=3840
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