***This is a 3rd-party extension of the DCPU specification.  The changes are as follows:
* Addition of three instructions: SMP, RMP, HWP, and HWU.
* Slightly modified how interrupts are handled for better hardware support.
* Addition of hot-swapping critieria.
* Added protection to changing IA.
***Justification for changes:
These changes make it more difficult for unintentional crashes to occur.  For instance, a
kernel in the current specification could be accidently corrupted by a user program, causing
the machine state to be extremely unstable.  Or, a small corruption could introduce a bug
in a very isolated area of the kernel, perhaps only affecting a program or two and being very
difficult to detect.  Additionally, a malicious program could introduce an infinite loop and
disable interrupts to crash the device.

With these changes, kernels and more could be made temporarily (or permenately) read-only,
preventing corruption.  Additionally, on multitasking systems, hardware usage could be
managed by the kernel, preventing conflict by locking down hardware use.  Hot-swapping is
included here merely for convenience.  With the protection of IA, it also adds added stability
by allowing a kernel or system interrupt to have a key-combination based safety mechanism
that could, under all circumstances, recover from a crashed program.


DCPU-16 Specification [3rd-party extension]
Copyright 1985 Mojang
Version 1.4



=== SUMMARY ====================================================================

* 16 bit words
* 0x10000 words of ram
* 8 registers (A, B, C, X, Y, Z, I, J)
* program counter (PC)
* stack pointer (SP)
* extra/excess (EX)
* interrupt address (IA)

In this document, anything within [brackets] is shorthand for "the value of the
RAM at the location of the value inside the brackets". For example, SP means
stack pointer, but [SP] means the value of the RAM at the location the stack
pointer is pointing at.

Whenever the CPU needs to read a word, it reads [PC], then increases PC by one.
Shorthand for this is [PC++]. In some cases, the CPU will modify a value before
reading it, in this case the shorthand is [++PC].

For stability and to reduce bugs, it's strongly suggested all multi-word
operations use little endian in all DCPU-16 programs, wherever possible.



=== INSTRUCTIONS ===============================================================

Instructions are 1-3 words long and are fully defined by the first word.
In a basic instruction, the lower five bits of the first word of the instruction
are the opcode, and the remaining eleven bits are split into a five bit value b
and a six bit value a.
b is always handled by the processor after a, and is the lower five bits.
In bits (in LSB-0 format), a basic instruction has the format: aaaaaabbbbbooooo

In the tables below, C is the time required in cycles to look up the value, or
perform the opcode, VALUE is the numerical value, NAME is the mnemonic, and
DESCRIPTION is a short text that describes the opcode or value.



--- Values: (5/6 bits) ---------------------------------------------------------
 C | VALUE     | DESCRIPTION
---+-----------+----------------------------------------------------------------
 0 | 0x00-0x07 | register (A, B, C, X, Y, Z, I or J, in that order)
 0 | 0x08-0x0f | [register]
 1 | 0x10-0x17 | [register + next word]
 0 |      0x18 | (PUSH / [--SP]) if in b, or (POP / [SP++]) if in a
 0 |      0x19 | [SP] / PEEK
 1 |      0x1a | [SP + next word] / PICK n
 0 |      0x1b | SP
 0 |      0x1c | PC
 0 |      0x1d | EX
 1 |      0x1e | [next word]
 1 |      0x1f | next word (literal)
 0 | 0x20-0x3f | literal value 0xffff-0x1e (-1..30) (literal) (only for a)
 --+-----------+----------------------------------------------------------------

* "next word" means "[PC++]". Increases the word length of the instruction by 1.
* By using 0x18, 0x19, 0x1a as PEEK, POP/PUSH, and PICK there's a reverse stack
  starting at memory location 0xffff. Example: "SET PUSH, 10", "SET X, POP"



--- Basic opcodes (5 bits) ----------------------------------------------------
 C | VAL  | NAME     | DESCRIPTION
---+------+----------+--------------------------------------------------------
 - | 0x00 | n/a      | special instruction - see below
 1 | 0x01 | SET b, a | sets b to a
 2 | 0x02 | ADD b, a | sets b to b+a, sets EX to 0x0001 if there's an overflow,
   |      |          | 0x0 otherwise
 2 | 0x03 | SUB b, a | sets b to b-a, sets EX to 0xffff if there's an underflow,
   |      |          | 0x0 otherwise
 2 | 0x04 | MUL b, a | sets b to b*a, sets EX to ((b*a)>>16)&0xffff (treats b,
   |      |          | a as unsigned)
 2 | 0x05 | MLI b, a | like MUL, but treat b, a as signed
 3 | 0x06 | DIV b, a | sets b to b/a, sets EX to ((b<<16)/a)&0xffff. if a==0,
   |      |          | sets b and EX to 0 instead. (treats b, a as unsigned)
 3 | 0x07 | DVI b, a | like DIV, but treat b, a as signed
 3 | 0x08 | MOD b, a | sets b to b%a. if a==0, sets b to 0 instead.
 1 | 0x09 | AND b, a | sets b to b&a
 1 | 0x0a | BOR b, a | sets b to b|a
 1 | 0x0b | XOR b, a | sets b to b^a
 2 | 0x0c | SHR b, a | sets b to b>>>a, sets EX to ((b<<16)>>a)&0xffff
   |      |          | (logical shift)
 2 | 0x0d | ASR b, a | sets b to b>>a, sets EX to ((b<<16)>>>a)&0xffff
   |      |          | (arithmetic shift) (treats b as signed)
 2 | 0x0e | SHL b, a | sets b to b<<a, sets EX to ((b<<a)>>16)&0xffff
 2 | 0x0f | MVI b, a | sets b to a, then increases I and J by 1
 2+| 0x10 | IFB b, a | performs next instruction only if (b&a)!=0
 2+| 0x11 | IFC b, a | performs next instruction only if (b&a)==0
 2+| 0x12 | IFE b, a | performs next instruction only if b==a
 2+| 0x13 | IFN b, a | performs next instruction only if b!=a
 2+| 0x14 | IFG b, a | performs next instruction only if b>a
 2+| 0x15 | IFA b, a | performs next instruction only if b>a (signed)
 2+| 0x16 | IFL b, a | performs next instruction only if b<a
 2+| 0x17 | IFU b, a | performs next instruction only if b<a (signed)
 - | 0x18 | -        |
 - | 0x19 | -        |
 3 | 0x1a | ADX b, a | sets b to b+a+EX, sets EX to 0x0001 if there is an over-
   |      |          | flow, 0x0 otherwise
 3 | 0x1b | SUX b, a | sets b to b-a+EX, sets EX to 0xFFFF if there is an under-
   |      |          | flow, 0x0 otherwise
 - | 0x1c | -        |
 - | 0x1d | -        |
 - | 0x1e | SMP b, a | sets the address range b-a to be read-only.  This is a
   |      |          | NOP unless executed from read-only memory or PC < 0x1000.
 2 | 0x1f | RMP b, a | sets the address range b-a to be writeable.  This is a
   |      |          | NOP unless executed from read-only memory or PC < 0x1000.
---+------+----------+----------------------------------------------------------

* The branching opcodes take one cycle longer to perform if the test fails
* Signed numbers are represented using two's complement.



Special opcodes always have their lower five bits unset, have one value and a
five bit opcode. In binary, they have the format: aaaaaaooooo00000
The value (a) is in the same six bit format as defined earlier.

--- Special opcodes: (6 bits) --------------------------------------------------
 C | VAL  | NAME  | DESCRIPTION
---+------+-------+-------------------------------------------------------------
 - | 0x00 | n/a   | reserved for future expansion
 3 | 0x01 | JSR a | pushes the address of the next instruction to the stack,
   |      |       | then sets PC to a
 - | 0x02 | -     |
 - | 0x03 | -     |
 - | 0x04 | -     |
 - | 0x05 | -     |
 - | 0x06 | -     |
 - | 0x07 | -     |
 4 | 0x08 | INT a | triggers a software interrupt with message a
 1 | 0x09 | IAG a | sets a to IA.  This is a NOP unless executed from read-only
   |      |       | memory or PC < 0x1000.
 1 | 0x0a | IAS a | sets IA to a.  This is a NOP unless executed from read-only
   |      |       | memory or PC < 0x1000.
 - | 0x0b | -     |
 - | 0x0c | -     |
 - | 0x0d | -     |
 - | 0x0e | -     |
 - | 0x0f | -     |
 2 | 0x10 | HWN a | sets a to number of connected hardware devices
 4 | 0x11 | HWQ a | sets A, B, C, X, Y registers to information about hardware a
   |      |       | a+b is a 32 bit word identifying the hardware type
   |      |       | c is the hardware revision
   |      |       | x+y is a 32 bit word identifying the manufacturer
 4+| 0x12 | HWI a | sends an interrupt to hardware a
 2 | 0x13 | HWP a | adds hardware protection to hardware a.  This is a NOP unless
   |      |       | executed from read-only memory or PC < 0x1000.
 2 | 0x14 | HWU a | removes hardware protection from hardware a.  This is a NOP
   |      |       | unless executed from read-only memory or PC < 0x1000.
 - | 0x15 | -     |
 - | 0x16 | -     |
 - | 0x17 | -     |
 - | 0x18 | -     |
 - | 0x19 | -     |
 - | 0x1a | -     |
 - | 0x1b | -     |
 - | 0x1c | -     |
 - | 0x1d | -     |
 - | 0x1e | -     |
 - | 0x1f | -     |
---+------+-------+-------------------------------------------------------------



=== INTERRUPTS =================================================================

The DCPU-16 will perform at most one interrupt between each instruction.

When IA is set to something other than 0, interrupts triggered on the DCPU-16
will push PC to the stack, followed by pushing A and B to the stack (in that order),
then set the PC to IA, A to the interrupt message, and B to the interrupting device
number. A well formed interrupt handler must pop A and B from the stack before
returning (popping PC from the stack)

If IA is set to 0, a triggered interrupt does nothing. Software interrupts still
take up two clock cycles, but immediately return, hardware interrupts are
ignored, with the hardware being notified of this. Some hardware may choose to
attempt to trigger the interrupt again at a later point.

The DCPU-16 has no way of knowing when an interrupt handler has finished, so if
an interrupt is triggered while an interrupt is being handled, the handler will
get called twice. Calling IAS 0 immediately at the start of the handler will
reliably prevent multiple concurrent interrupts.



=== HARDWARE ===================================================================

The DCPU-16 supports up to 65534 connected hardware devices. These devices can
be anything from additional storage, sensors, monitors or speakers.
How to control the hardware is specified per hardware device, but the DCPU-16
supports a standard enumeration method for detecting connected hardware via
the HWN, HWQ and HWI instructions.

Interrupts sent to hardware can't contain messages, can take additional cycles,
and can read or modify any registers or memory adresses on the DCPU-16. This
behavior changes per hardware device and is described in the hardware's
documentation.

Hardware must NOT start modifying registers or ram on the DCPU-16 before at
least one HWI call has been made to the hardware.

When hardware is disconnected from the CPU (hot-swapped), an interrupt is sent
with a B set to 0xFFFF.  The message (A) is the device number that has been
disconnected.  The same proceduce is used for devices when connected, except
that B is set to 0xFFFE.

Hardware that is "protected" may only have interrupts triggered from read-only
memory.