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  1. // 00 -> AND, 01 -> OR, 10 -> NOR, 11 -> XOR
  2. module logicunit(out, A, B, control);
  3.     output      out;
  4.     input       A, B;
  5.     input [1:0] control;
  6.     wire l, m, n, p;
  7.  
  8.     and a1(l, A, B);
  9.     or o1(m, A, B);
  10.     nor n1(n, A, B);
  11.     xor x1(p, A, B);
  12.  
  13.     mux4 mx1(out, l, m, n, p, control);
  14. endmodule // logicunit
  15.  
  16.  
  17.  
  18. module logicunit_test;
  19.     // exhaustively test your logic unit implementation by adapting mux4_tb.v
  20.     // cycle through all combinations of A, B, C, D every 16 time units
  21.     reg A = 0;
  22.     always #1 A = !A;
  23.     reg B = 0;
  24.     always #2 B = !B;
  25.  
  26.     reg [1:0] control = 0;
  27.     initial begin
  28.         $dumpfile("logicunit.vcd");
  29.         $dumpvars(0, logicunit_test);
  30.  
  31.         // control is initially 0
  32.         # 16 control = 1; // wait 16 time units (why 16?) and then set it to 1
  33.         # 16 control = 2; // wait 16 time units and then set it to 2
  34.         # 16 control = 3; // wait 16 time units and then set it to 3
  35.         # 16 $finish; // wait 16 time units and then end the simulation
  36.     end
  37.  
  38.     wire out;
  39.     logicunit l1(out, A, B, control);
  40.  
  41.     // you really should be using gtkwave instead
  42.     /*
  43.     initial begin
  44.         $display("A B C D s o");
  45.         $monitor("%d %d %d %d %d %d (at time %t)", A, B, C, D, control, out, $time);
  46.     end
  47.     */
  48. endmodule // logicunit_test
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