library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sender_AL is
		port(
				CLOCK_50			: in std_logic;
				KEY				: in std_logic_vector(3 downto 0);
				SW					: in std_logic_vector(17 downto 0);
				GPIO				: inout std_logic_vector(35 downto 0);
				LEDR				: out std_logic_vector(17 downto 0);
				LEDG				: out std_logic_vector(7 downto 0)
			);
end sender_AL;

architecture RTL of sender_AL is

	signal hallo_enable		: std_logic;
	signal hallo				: std_logic;
	signal resetn				: std_logic;
	signal sender				: std_logic;
	signal mottat_blink		: std_logic;
	signal vippe_a, vippe_b : std_logic;

	signal start_teller, baud_enable_m, baud_enable_s : std_logic;

	type sender_state_type is (s_idle, s_transmit, s_shift_out, s_finish, s_wait);
	signal sender_state : sender_state_type;

	signal send_shift_register  : std_logic_vector(9 downto 0);

	constant START_BIT : std_logic := '0';
	constant STOPP_BIT : std_logic := '1';

	signal data_inn, data_ut : std_logic;
	signal start_sender, start_q, start_qq : std_logic;

	type mottak_state_type is (s_idle, s_wait_for_sender, s_shift_in, s_offload, s_error);
	signal mottak_state : mottak_state_type;

	signal data_inn_q, data_inn_qq, data_inn_qqq : std_logic;
	signal error : std_logic;
	signal mottak_shift_reg : std_logic_vector(9 downto 0);
	signal motatt_data : std_logic_vector(7 downto 0);


	component Enable_gen Is
	Port ( clock_50 : in std_logic;
			 resetn : in std_logic;
			 velg_enable:in std_logic_vector(2 downto 0);
			 Enable: out std_logic);
	End component;


	component reset_sync is
	port(
			clk, reset_key3	: in std_logic;
			reset_clk	: out std_logic

		);
end component reset_sync;

component baudrate_gen is
		port(
				CLOCK_50			: in std_logic;
				resetn			: in std_logic;
				velg_baudrate  : in std_logic_vector(2 downto 0);

				start_teller	: in std_logic;
				baud_enable_m  : out std_logic;
				baud_enable_s  : out std_logic

		);
end component baudrate_gen;

begin

	Enable_gen_inst : component Enable_gen
		port map(
			clock_50        => CLOCK_50,
			resetn     => resetn,
			velg_enable => "111",
			Enable => hallo_enable

		);

		reser_syn_inst : component reset_sync
			port map(
				clk        => CLOCK_50,
			reset_key3 => KEY(3),
			reset_clk  => resetn
		);

		-- lag lokalt blinkesignal
		p_hallo : process (CLOCK_50) is
		begin
			if rising_edge(CLOCK_50) then
				if resetn = '0' then
					hallo <= '0';
				elsif hallo_enable = '1' then
					hallo <= not hallo;
				end if;
			end if;
		end process p_hallo;

	LEDR(17) <= hallo;

	sender <= SW(17);
	LEDG(0) <= sender;
	LEDG(7) <= mottat_blink;


	p_send_motta_hallo : process (CLOCK_50) is
	begin
		if rising_edge(CLOCK_50) then
			if sender = '1' then
				GPIO(1) <= hallo;
				mottat_blink <= '0';
			else
				-- mottar hallo
				GPIO(1) <= 'Z';
				vippe_a <= GPIO(1);
				vippe_b <= vippe_a;
				mottat_blink <= vippe_b;
			end if;
		end if;
	end process;

	baudrate_gen_inst : component baudrate_gen
		port map(
				CLOCK_50			=>		CLOCK_50,
				resetn		 	=>		resetn,
				velg_baudrate	=>		SW(16 downto 14),
				start_teller	=>		start_teller,
				baud_enable_m	=>		baud_enable_m,
				baud_enable_s	=>		baud_enable_s
			);

	data_inn <= GPIO(7) when sender = '0' else '1';
	GPIO(7)  <= data_ut when sender = '1' else 'Z';

	p_start_teller : process(CLOCK_50) is  --data inn
	begin
		if rising_edge(CLOCK_50) then
			if resetn = '0' then
				start_teller	<= '0';
				data_inn_q		<= '0';
				data_inn_qq		<= '0';
				data_inn_qqq	<= '0';

			else
				start_teller <= '0';
				data_inn_q <= data_inn;
				data_inn_qq <= data_inn_q;
				data_inn_qqq <= data_inn_qq;
				if data_inn_qqq = '1' and data_inn_qq = '0' then
					--fallende flanke
					if mottak_state = s_wait_for_sender then
						start_teller <= '1';
					end if;
				end if;
			end if;
		end if;
	end process p_start_teller;


	start_sender <= KEY(0);

	p_synk_start_sender : process(CLOCK_50) is
	begin
		if rising_edge(CLOCK_50) then
			if resetn = '0' then
				start_q   <=  '0';
				start_qq  <=  '0';
			else
				start_q  <= not start_sender;
				start_qq <= start_sender;
			end if;
		end if;
	end process p_synk_start_sender;


	p_sender_tilstandsmaskin : process(CLOCK_50) is
	begin
		if rising_edge(CLOCK_50) then
			if resetn = '0' then
				sender_state <= s_idle;
			else

				if baud_enable_s = '1' and sender = '1' then
					case sender_state is
						when s_idle =>
							data_ut <= '1';
								send_shift_register <= (others => '0');
									if start_qq = '1' then
										sender_state <= s_transmit;
									end if;

						when s_transmit =>
							data_ut <= '1';
							send_shift_register <= STOPP_BIT & SW(8 downto 1) & START_BIT;
								if baud_enable_s = '1' then
									sender_state <= s_shift_out;
							end if;

						when s_shift_out =>
							if baud_enable_s = '1' then
								if send_shift_register = "0000000000" then
									sender_state <= s_finish;
									data_ut <= '1';
								else
									data_ut <= send_shift_register(0);
									send_shift_register <= '0' & send_shift_register(9 downto 1);

								end if;
							end if;
						when s_finish =>
							data_ut <= '1';
							if baud_enable_s = '1' then
								sender_state <= s_wait;
							end if;

						when s_wait =>
							data_ut <= '1';
							if baud_enable_s = '1' then
								sender_state <= s_transmit;
							end if;
					end case;
				end if;
			end if;
		end if;
	end process;


	p_mottak_tilstandsmaskin : process(CLOCK_50) is
	begin
		if rising_edge(CLOCK_50) then
			if resetn = '0' then
				motatt_data <= "00000000";
				mottak_state <= s_idle;
				error <= '0';
			else
				if sender = '0' then
				case mottak_state is

					when s_idle =>
						error <= '0';
						mottak_shift_reg <= "1000000000";
						if data_inn_qq = '1' then
							mottak_state <= s_wait_for_sender;
						end if;

					when s_wait_for_sender =>
						if start_teller = '1' then
							mottak_state <= s_shift_in;
						end if;

					when s_shift_in =>
						if mottak_shift_reg(0) = '1' and mottak_shift_reg(9) = '0' then
							-- dette skal aldri skje
							mottak_state <= s_error;
						elsif mottak_shift_reg(0) = '1' and mottak_shift_reg(9) = '1' then
							-- mottat alle databit of stoppbit
							mottak_state <= s_offload;
						elsif baud_enable_m = '1' then
							mottak_shift_reg <= data_inn_qq & mottak_shift_reg(9 downto 1);
						end if;

					when s_offload =>
						motatt_data <= mottak_shift_reg(8 downto 1);
						mottak_state <= s_idle;

					when s_error =>
						error <= '1';
				end case;
			end if;
			end if;
		end if;
	end process p_mottak_tilstandsmaskin;

	LEDR(16) <= error;
	LEDR(8 downto 1) <= motatt_data;


end architecture RTL;