`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    09:42:28 10/28/2019
// Design Name:
// Module Name:    Project2Verilog
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Project2Verilog(
 input GCLK20,

	 output DA,
	 output DB,
	 output DC,
	 output DD,
	 output DE,
	 output DF,
	 output DG,

	 output S1,
	 output S2,
	 output S3,
	 output S4
	 );


	 reg [25:0] counter1;
	 reg[14:0] counter2;
	 reg[15:0] number;
	 reg[3:0] menu;
	 reg[6:0] set;
	 reg[3:0] buff;
    always@(posedge GCLK20)
	 begin
     counter2<=counter2+14'b1;
	  counter1<=counter1+25'b1;
	  if(counter1==25'b0)
	  number=number+16'b1;
	  end


always@*
begin
case(buff [3:0])
0000: set[6:0]=7'b00000001;
0001: set[6:0]=7'b1001111;
0010: set[6:0]=7'b0010010;
0011: set[6:0]=7'b0000110;
0100: set[6:0]=7'b1001100;
0101: set[6:0]=7'b0100100;
0111: set[6:0]=7'b0100000;
1000: set[6:0]=7'b0001111;
1001: set[6:0]=7'b0000000;
1010: set[6:0]=7'b0000100;
1011: set[6:0]=7'b1100000;
1100: set[6:0]=7'b0110001;
1101: set[6:0]=7'b1000010;
1110: set[6:0]=7'b0110000;
1111: set[6:0]=7'b0111000;
endcase
end



always@*
begin
case( counter2[14:13] )
2'b00:
begin
menu=4'b1110;
buff<=number[15:12];
end
2'b01:
begin
menu=4'b1101;
buff<=number[11:8];
end
2'b10:
begin
menu=4'b1011;
buff<=number[7:3];
end
2'b11:
begin
menu=4'b0111;
buff<=number[3:0];
end
endcase
end

assign S1=menu[3];
assign S2=menu[2];
assign S3=menu[1];
assign S4=menu[0];

    assign DA=set[6];
	 assign DB=set[5];
	 assign DC=set[4];
	 assign DD=set[3];
	 assign DE=set[2];
	 assign DF=set[1];
	 assign DG=set[0];

endmodule