Increasing the CPU frequency:

The sequence to go from Range 2 to Range 1 is:
 1. Program the VOS bits to “01” in the PWR_CR1 register.
 2. Wait until the VOSF flag is cleared in the PWR_SR2 register.
 3. Adjust number of wait states according new frequency target in Range 1 (LATENCY bits in the FLASH_ACR).
 4. Increase the system frequency

 1. Program the new number of wait states to the LATENCY bits in the Flash access control register (FLASH_ACR).
 2. Check that the new number of wait states is taken into account to access the Flash memory
	by reading the FLASH_ACR register.
 3. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register.
 4. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR.
 5. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are taken into account
    by reading the clock source status (SWS bits) or/and the AHB prescaler value (HPRE bits),
	respectively, in the RCC_CFGR register.

Decreasing the CPU frequency:
 1. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register.
 2. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR.
 3. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are taken into account
    by reading the clock source status (SWS bits) or/and the AHB prescaler value (HPRE bits),
	respectively, in the RCC_CFGR register.

 4. Program the new number of wait states to the LATENCY bits in Flash access control register (FLASH_ACR).
 5. Check that the new number of wait states is used to access the Flash memory by reading the FLASH_ACR register.

The sequence to go from Range 1 to Range 2 is:
 1. Reduce the system frequency to a value lower than 26 MHz
 2. Adjust number of wait states according new frequency target in Range 2 (LATENCY bits in the FLASH_ACR).
 3. Program the VOS bits to “10” in the PWR_CR1 register.