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Aug 22nd, 2021
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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qca955x.dtsi"
  3.  
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/input/input.h>
  6.  
  7. / {
  8. compatible = "asus,rt-ac55u", "qca,qca9557";
  9. model = "ASUS RT-AC55U";
  10.  
  11. aliases {
  12. led-boot = &led_power;
  13. led-failsafe = &led_power;
  14. led-running = &led_power;
  15. led-upgrade = &led_power;
  16. };
  17.  
  18. keys {
  19. compatible = "gpio-keys";
  20.  
  21. reset {
  22. label = "reset";
  23. gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
  24. linux,code = <KEY_RESTART>;
  25. debounce-interval = <60>;
  26. };
  27. wps {
  28. label = "wps";
  29. gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
  30. linux,code = <KEY_WPS_BUTTON>;
  31. debounce-interval = <60>;
  32. };
  33. };
  34.  
  35. leds {
  36. compatible = "gpio-leds";
  37.  
  38. led_power: power {
  39. label = "blue:power";
  40. gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
  41. };
  42.  
  43.  
  44. wifi2g {
  45. label = "blue:wifi2g";
  46. gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
  47. linux,default-trigger = "phy1tpt";
  48. };
  49.  
  50.  
  51. wps {
  52. label = "blue:wps";
  53. gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
  54. };
  55. };
  56. };
  57.  
  58. &nand {
  59. status="okay";
  60.  
  61. partitions {
  62. compatible="fixed-partitions";
  63. #address-cells = <1>;
  64. #size-cells = <1>;
  65.  
  66. partition@0 {
  67. label = "Bootloader";
  68. reg = <0x000000000000 0x000e0000>;
  69. };
  70. partition@000000100000 {
  71. label = "ubi";
  72. reg = <0x000000100000 0x07e00000>;
  73. };
  74. caldata: partition@000007f00000 {
  75. label = "caldata";
  76. reg = <0x000007f00000 0x00010000>;
  77. };
  78. };
  79. };
  80.  
  81.  
  82. &wmac {
  83. status="okay";
  84. mtd-cal-data = <&caldata 0x1000>;
  85. };
  86. &pcie0 {
  87. status = "okay";
  88.  
  89. wifi@0,0 {
  90. compatible = "qcom,ath10k";
  91. reg = <0 0 0 0 0>;
  92. };
  93. };
  94.  
  95. &eth0 {
  96. status = "okay";
  97.  
  98. pll-data = <0xa6000000 0x00000101 0x00001616>;
  99. phy-handle = <&phy17>;
  100.  
  101. fixed-link {
  102. speed = <1000>;
  103. full-duplex;
  104. };
  105. };
  106.  
  107. &eth1 {
  108. status = "okay";
  109.  
  110. pll-data = <0x03000101 0x00000101 0x00001616>;
  111. phy-handle = <&phy1>;
  112.  
  113. fixed-link {
  114. speed = <1000>;
  115. full-duplex;
  116. };
  117. };
  118.  
  119.  
  120.  
  121. &pcie1 {
  122. status="okay";
  123. };
  124.  
  125. &usb_phy0 {
  126. status="okay";
  127. };
  128.  
  129. &usb0 {
  130. status="okay";
  131. };
  132.  
  133.  
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