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  1. ; ===========================================================================
  2. ; ---------------------------------------------------------------------------
  3. ; Start of ROM data
  4. ; ---------------------------------------------------------------------------
  5.  
  6. StartRom: dc.l $4EA10001+($07+$04) ; prepare TMSS address in the stack
  7. moveq #$00,d4 ; clear d4
  8. ori.b #$00,d4 ; a filler instruction, must be ori.b, must be d4 (The immediate value can be whatever necessary though).
  9.  
  10. ; --- Soft Reset ---
  11.  
  12. tst.w (sp) ; has control port C been initialised? (last port to be initialised)
  13. bne.w SG_Reset ; if all ports have been initialised, branch
  14.  
  15. ; --- TMSS ---
  16.  
  17. move.b -($07+$04)(sp),d3 ; load hardware version
  18. asl.b #$04,d3 ; get only hardware version ID
  19. beq.s SG_NoTMSS ; if it's version 0, branch
  20. move.l (ConsoleName).w,($3FFF-($07+$04))(sp) ; save SEGA to TMSS chip
  21.  
  22. SG_NoTMSS:
  23.  
  24. ; --- VDP DMA wait/Latch reset ---
  25.  
  26. lea ($C00000).l,a5 ; load VDP data port
  27. lea $04(a5),a6 ; load VDP control port
  28.  
  29. SG_WaitDMA:
  30. move.w (a6),ccr ; load status (this resets the 2nd write flag too)
  31. bvs.s SG_WaitDMA ; if the VDP DMA busy flag was set (bit 1), branch to wait til finished...
  32.  
  33. ; --- VDP Register Setup & VRAM Clear ---
  34.  
  35. lea (SG_SetupList).w,a0 ; load VDP register list
  36. movem.w (a0)+,d1/d2/d5/a1 ; load number of entries, 80XX value, 0100 for advancing (and for Z80 later), VDP reg RAM
  37. lea (a1),a2 ; copy start register address as end RAM address
  38.  
  39. SG_SetupVDP:
  40. move.w d2,(a6) ; set VDP register
  41. move.w d2,(a1)+ ; ...and save to RAM storage
  42. add.w d5,d2 ; advance register ID
  43. move.b (a0)+,d2 ; load next register value
  44. dbf d1,SG_SetupVDP ; repeat for all registers
  45. move.l (a0)+,(a6) ; set DMA fill destination
  46. move.w d4,(a5) ; set DMA fill value (0000)
  47.  
  48. ; --- 68k RAM Clear ---
  49.  
  50. move.w #SG_InitStack&$FFFF,-(a2) ; set first return address to the stack
  51. move.w a2,d1 ; copy address (for size of remaining 68k RAM)
  52. subq.w #$01,d1 ; minus 1 (for dbf)
  53.  
  54. SG_ClearRAM:
  55. move.b d4,-(a2) ; clear entire RAM
  56. dbf d1,SG_ClearRAM ; repeat until entire RAM is cleared
  57.  
  58. ; --- Loading Z80 related data (for Part 2) ---
  59.  
  60. movem.l (a0)+,d0/a1/a3-a4 ; load Z80 RAM addresses & flag settings
  61. move.w d5,(a3) ; request Z80 stop (ON)
  62.  
  63. ; --- CRAM/VSRAM Clear ---
  64.  
  65. neg.w d1 ; convert FFFF to 0001 ; number of times to run (Twice: CRAM first, VSRAM second)
  66.  
  67. SG_ClearCRAM:
  68. move.l (a0)+,(a6) ; set VDP to VSRAM/CRAM write mode
  69. moveq #$3F,d3 ; set repeat times
  70.  
  71. SG_ClearVSRAM:
  72. move.w d4,(a5) ; clear VSRAM/CRAM (done by word to slow the 68k down enough to stop the Z80 in time)
  73. dbf d3,SG_ClearVSRAM ; repeat until entire VSRAM/CRAM is cleared
  74. move.w d2,-(sp) ; initialise port B, then A (C will be done last)
  75. dbf d1,SG_ClearCRAM ; repeat routine (VSRAM is done, CRAM is next)
  76.  
  77. ; --- Jumping to part 2 ---
  78.  
  79. move.w d5,(a4) ; request Z80 reset (OFF)
  80.  
  81. bra.s SG_Continue ; branch to part 2
  82.  
  83. ; ---------------------------------------------------------------------------
  84. ; Setup information
  85. ; ---------------------------------------------------------------------------
  86. ; align $006C
  87. ; ---------------------------------------------------------------------------
  88.  
  89. dc.l R_HBlankInt ; H-blank address
  90. SG_CounterSum: dc.l -$01234567 ; counter checksum
  91. dc.l R_VBlankInt ; V-blank address
  92.  
  93. SG_SetupList: dc.w $0018-1 ; number of VDP registers to write
  94. dc.w $8000|%00000100 ; 00LH 01CD - Leftover SMS bar (0N|1Y) | H-Interrupt (0N|1Y) | H,V Counter (0N|1Y) | Disable video signal (0N|1Y)
  95. dc.w $0100 ; VDP Reg increment value & opposite initialisation flag for Z80
  96. dc.w (R_VDPReg80&$FFFF) ; VDP register RAM storage area
  97. dc.b %00010100 ; SDVM P100 - SMS mode (0N|1Y) | Display (0N|1Y) | V-Interrupt (0N|1Y) | DMA (0N|1Y) | V-resolution (0-1C|1-1E)
  98. dc.b ((($C000)>>$0A)&$FF) ; 00FE DCBA - Scroll Plane A Map Table VRam address
  99. dc.b ((($D000)>>$0A)&$FF) ; 00FE DCB0 / 00FE DC00 (20 Resolution) - Window Plane A Map Table VRam address
  100. dc.b ((($E000)>>$0D)&$FF) ; 0000 0FED - Scroll Plane B Map Table VRam address
  101. dc.b ((($BC00)>>$09)&$FF) ; 0FED CBA9 / 0FED CBA0 (20 Resolution) - Sprite Plane Map Table VRam address
  102. dc.b $00 ; 0000 0000 - Unknown/Unused Register
  103. dc.b $00 ; 00PP CCCC - Backdrop Colour: Palette Line 0/Colour ID 0
  104. dc.b $00 ; 0000 0000 - Unknown/Unused Register
  105. dc.b $00 ; 0000 0000 - Unknown/Unused Register
  106. dc.b $DF ; 7654 3210 - H-Interrupt Register
  107. dc.b %00000000 ; 0000 EVHH - External Interrupt (0N|1Y) | V-Scroll: (0-Full|1-2Celled) | H-Scroll: (00-Full|10-Celled|11-Sliced)
  108. dc.b %10000001 ; APHE SNNB - H-resol (0N|1Y) | Pixel int (0N|1Y) | H-sync (0N|1Y) | Extern-pix (0N|1Y) | S/H (0N|1Y) | Interlace (00N|01Y|11-Split) | H-resol (0-20|1-28)
  109. dc.b ((($B800)>>$0A)&$FF) ; 00FE DCBA - Horizontal Scroll Table VRam address
  110. dc.b $00 ; 0000 0000 - Unknown/Unused Register
  111. dc.b $02 ; 7654 3210 - Auto Increament: By 2
  112. dc.b %00000001 ; 00VV 00HH - Plane Y Size (00-20|01-40|11-80) | Plane X size (00-20|01-40|11-80)
  113. dc.b $00 ; 7654 3210 - Window Horizontal Position
  114. dc.b $00 ; 7654 3210 - Window Vertical Position
  115. dc.b $FF ; 7654 3210 - DMA Fill Size (FFFF bytes)
  116. dc.b $FF ; FEDC BA98 - ''
  117. dc.b $00 ; 7654 3210 - DMA Fill Source (800000 Fill mode)
  118. dc.b $00 ; FEDC BA98 - ''
  119. dc.b $80 ; D654 3210 - '' D = DMA
  120.  
  121. dc.b %01000000 ; control port initialisation flags
  122. dc.l $40000080 ; DMA Fill destination
  123.  
  124. ; --- Z80 register data ---
  125.  
  126. dc.w $000E,(($2000-$02)-$01) ; d0 ; red checksum error colour & Z80 RAM size
  127. dc.l $A00000 ; a1 ; load Z80 RAM address
  128. dc.l $A11100 ; a3 ; load Z80 bus access port
  129. dc.l $A11200 ; a4 ; load Z80 reset port
  130.  
  131. ; --- VSRAM/CRAM ---
  132.  
  133. dc.l $40000010 ; VSRAM write mode
  134. dc.l $C0000000 ; CRAM write mode
  135.  
  136. dc.b $9F,$BF,$DF,$FF ; PSG mute values (PSG 1 to 4)
  137. dc.b $F3,$C3 ; di & jp instructions
  138.  
  139. ; ---------------------------------------------------------------------------
  140. ; Initialising the stack before starting the game
  141. ; ---------------------------------------------------------------------------
  142.  
  143. SG_InitStack:
  144. pea (ResetGame).w ; set "reset" routine address (when reset is pressed, this routine will run instead)
  145. bra.w StartGame ; branch to starting routine
  146.  
  147. ; ---------------------------------------------------------------------------
  148. ; Continue (Part 2)
  149. ; ---------------------------------------------------------------------------
  150.  
  151. SG_Continue:
  152.  
  153. ; --- PSG Reset ---
  154.  
  155. moveq #$04-1,d3 ; set number of PSG channels to mute (for Part 2)
  156.  
  157. SG_MutePSG:
  158. move.b (a0)+,$0D(a6) ; set the PSG channel volume to null (No sound)
  159. dbf d3,SG_MutePSG ; repeat for all channels
  160.  
  161. ; --- Z80 Setup & YM2612 Reset ---
  162.  
  163. ; btst.b d4,(a3) ; No need, it was stopped a... ; has the Z80 stopped yet?
  164. ; bne.s *-$08 ; ...long time ago (see above) ; if not, branch
  165. move.b (a0)+,(a1)+ ; write di (disable interrupts) instruction
  166. move.b (a0)+,(a1)+ ; write jp (jump) instruction (the 00's after will jump to 0)
  167.  
  168. SG_ClearZ80:
  169. move.b d4,(a1)+ ; clear Z80 space
  170. dbf d0,SG_ClearZ80 ; repeat til done
  171. move.w d4,(a4) ; request Z80 reset (ON)
  172.  
  173. ; --- ROM Checksum (is also enough delay for Z80 reset) ---
  174.  
  175. move.l (ROMFinish).w,a0 ; load end ROM address
  176.  
  177. SG_CheckSum:
  178. add.l -(a0),d4 ; move back and add a long-word
  179. move.l a0,d3 ; copy address to d3
  180. bne.s SG_CheckSum ; if the address is not 0, branch
  181. cmpi.l #$01234567,d4 ; is the ROM sum correct? (Modify this long-word externally)
  182. beq.s SG_NoLockSum ; if not, branch and loop endlessly
  183. move.l d0,(a5) ; write red colour to CRAM backdrop
  184. bra.s * ; branch endlessly for checksum error (trap/loop)
  185.  
  186. SG_NoLockSum:
  187. move.w d5,(a4) ; request Z80 reset (OFF)
  188. move.w a0,(a3) ; request Z80 stop (OFF)
  189.  
  190. ; --- I/O port initialisation (Must be done last) ---
  191.  
  192. move.w d2,$04(sp) ; initialise port C (last one)
  193.  
  194. ; --- Final ---
  195.  
  196. SG_Reset:
  197. movea.w #(R_StackSP&$FFFF),sp ; set stack address
  198.  
  199. SG_Return:
  200. rts ; return
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