input [3:0] remote_full_flags;
input [3:0] local_full_flags;

wire [7:0] full_flags;
assign full_flags = {remote_full_flags, local_full_flags};

reg [2:0] leading_ones;

always @(*) begin
    casez(full_flags << addr) begin
        8'b0???????: leading_ones = 0;
        8'b10??????: leading_ones = 1;
        8'b110?????: leading_ones = 2;
        8'b1110????: leading_ones = 3;
        8'b11110???: leading_ones = 4;
        8'b111110??: leading_ones = 5;
        8'b1111110?: leading_ones = 6;
        8'b11111110: leading_ones = 7;
        8'b11111111: begin
            leading_ones = 0;
            all_full = 1;
        end
    endcase
end

reg [1:0] addr;

initial
    addr = 2'b00;

always@(posedge clk) begin
  if (all_full)
    addr <= addr + 1 + leading_ones;
end