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- NOTICE: BL2: v2.4(release):LSDK-21.08-8-g98ed7bc18
- NOTICE: BL2: Built : 10:12:27, Sep 3 2023
- NOTICE: UDIMM CT32G4SFD832A.M16F
- NOTICE: DDR PMU Hardware version-0x1210
- NOTICE: DDR PMU Firmware vision-0x1001 (vA-2019.04)
- NOTICE: DDR4 UDIMM with 2-rank 64-bit bus (x8)
- NOTICE: 64 GB DDR4, 64-bit, CL=17, ECC off, 256B, CS0+CS1
- NOTICE: BL2: Booting BL31
- NOTICE: BL31: v2.4(release):LSDK-21.08-8-g98ed7bc18
- NOTICE: BL31: Built : 10:12:27, Sep 3 2023
- NOTICE: Welcome to lx2160acex7 BL31 Phase
- U-Boot 2021.04-00040-g8288c790f (Sep 03 2023 - 10:12:25 +0000)
- SoC: LX2160ACE Rev2.0 (0x87360020)
- Clock Configuration:
- CPU0(A72):2000 MHz CPU1(A72):2000 MHz CPU2(A72):2000 MHz
- CPU3(A72):2000 MHz CPU4(A72):2000 MHz CPU5(A72):2000 MHz
- CPU6(A72):2000 MHz CPU7(A72):2000 MHz CPU8(A72):2000 MHz
- CPU9(A72):2000 MHz CPU10(A72):2000 MHz CPU11(A72):2000 MHz
- CPU12(A72):2000 MHz CPU13(A72):2000 MHz CPU14(A72):2000 MHz
- CPU15(A72):2000 MHz
- Bus: 700 MHz DDR: 2400 MT/s
- Reset Configuration Word (RCW):
- 00000000: 50636338 24500050 00000000 00000000
- 00000010: 00000000 0e010000 00000000 00000000
- 00000020: 10c001a0 00002580 00000000 08000086
- 00000030: 09240000 00000001 00000000 00000000
- 00000040: 00000000 00000000 00000000 00000000
- 00000050: 00000000 00000000 00000000 00000000
- 00000060: 00000000 00000000 00027000 00000000
- 00000070: 08a80001 00151020
- Model: SolidRun LX2160ACEX7 COM express type 7 based board
- Board: LX2160ACE Rev2.0-CEX7, SD
- SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 100MHz
- SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz
- SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz
- DRAM: 63.9 GiB
- DDR 63.9 GiB (DDR4, 64-bit, CL=17, ECC off)
- DDR Controller Interleaving Mode: 256B
- DDR Chip-Select Interleaving Mode: CS0+CS1
- dev_get_priv: null device
- dev_get_priv: null device
- Using SERDES1 Protocol: 8 (0x8)
- Using SERDES2 Protocol: 5 (0x5)
- Using SERDES3 Protocol: 2 (0x2)
- PCIe1: pcie@3400000 disabled
- PCIe2: pcie@3500000 disabled
- PCIe3: pcie@3600000 Root Complex: x4 gen3
- PCIe4: pcie@3700000 disabled
- PCIe5: pcie@3800000 Root Complex: no link
- PCIe6: pcie@3900000 disabled
- WDT: Started with servicing (30s timeout)
- MMC: FSL_SDHC: 0, FSL_SDHC: 1
- Loading Environment from MMC... *** Warning - bad CRC, using default environment
- EEPROM: TlvInfo v1 len=6
- In: serial_pl01x
- Out: serial_pl01x
- Err: serial_pl01x
- SEC0: RNG instantiated
- fsl_board_late_init
- Net:
- Warning: DPMAC3@xgmii (eth0) using random MAC address - 8e:cb:d5:27:6b:ac
- Warning: DPMAC4@xgmii (eth1) using random MAC address - d6:76:c0:5b:f1:ac
- Warning: DPMAC5@xgmii (eth2) using random MAC address - 06:25:13:46:ee:44
- Warning: DPMAC6@xgmii (eth3) using random MAC address - 8e:c6:df:f9:3a:5b
- Warning: DPMAC7@xgmii (eth4) using random MAC address - f2:df:bc:65:35:07
- Warning: DPMAC8@xgmii (eth5) using random MAC address - 5a:1d:2e:06:8e:a5
- Warning: DPMAC9@xgmii (eth6) using random MAC address - d2:5b:3d:2e:9e:4c
- Warning: DPMAC10@xgmii (eth7) using random MAC address - 6a:9c:f6:5d:84:20
- Warning: DPMAC17@rgmii-id (eth8) using random MAC address - 06:83:20:90:3e:6d
- eth0: DPMAC3@xgmii, eth1: DPMAC4@xgmii, eth2: DPMAC5@xgmii, eth3: DPMAC6@xgmii, eth4: DPMAC7@xgmii, eth5: DPMAC8@xgmii,
- eth6: DPMAC9@xgmii, eth7: DPMAC10@xgmii, eth8: DPMAC17@rgmii-id [PRIME]
- MMC read: dev # 0, block # 20480, count 4608 ... 4608 blocks read: OK
- MMC read: dev # 0, block # 28672, count 2048 ... 2048 blocks read: OK
- crc32+
- fsl-mc: Booting Management Complex ... SUCCESS
- fsl-mc: Management Complex booted (version: 10.37.0, boot status: 0x1)
- Hit any key to stop autoboot: 0
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