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### -----------------------------------------------------------------------------
### CMAC example design-level XDC file
### -----------------------------------------------------------------------------

create_clock -period 10.000 [get_ports init_clk_p]

create_clock -period 6.400 [get_ports gt_ref_clk_p]
#set_property IOSTANDARD DIFF_SSTL15 [get_ports gt_ref_clk_p]

### Transceiver Reference Clock Placement
### Transceivers should be adjacent to allow timing constraints to be met easily.
### Full details of available transceiver locations can be found in the appropriate
### Transceiver User Guide, or use the Transceiver Wizard.

### These are sample constraints, please use correct constraints for your device
### As per GT recommendation, gt_ref_clk should be connected to the middle quad

### Incase of VCU108-REV-1.0 Evaluation board with xcvu095-ffva2104-2-e device,
### if user selects CAUI10 GTY default gui configuration with CMAC core as CMAC_SITE_X0Y0
### and GT group X0Y4~X0Y13, the gt_ref_clk pin location is given below
### For other configuration / CMAC and GT locations, update the gt_ref_clk pin location accordingly
### and un-comment the below line
#set_property PACKAGE_PIN AK38 [get_ports gt_ref_clk_p]



### Change these IO constraints as per your board and device
### For better placement, please LOC the IO's in the same GT SLR region

### Below IO Loc XDC constraints are for VCU108-REV-1.0 Evaluation board
### with xcvu095-ffva2104-2-e-es2 device

### For init_clk input pin assignment, if single-ended clock is not available
### on the board, user has to instantiate IBUFDS in Example Design to convert
### the differential clock to single-ended clock and make the necessary changes
#set_property LOC AV33 [get_ports init_clk]
#set_property LOC E34 [get_ports sys_reset]
#set_property LOC C38 [get_ports send_continuous_pkts]
#set_property LOC AW27 [get_ports lbus_tx_rx_restart_in]
#set_property LOC BC40 [get_ports simplex_mode_rx_aligned]
#set_property LOC AT32 [get_ports tx_done_led]
#set_property LOC AY30 [get_ports tx_busy_led]
#set_property LOC BB32 [get_ports tx_gt_locked_led]

set_property IOSTANDARD LVCMOS18 [get_ports sys_reset]
set_property IOSTANDARD LVCMOS18 [get_ports send_continuous_pkts]
set_property IOSTANDARD LVCMOS18 [get_ports lbus_tx_rx_restart_in]
set_property IOSTANDARD LVCMOS18 [get_ports simplex_mode_rx_aligned]
set_property IOSTANDARD LVCMOS18 [get_ports tx_done_led]
set_property IOSTANDARD LVCMOS18 [get_ports tx_busy_led]
set_property IOSTANDARD LVCMOS18 [get_ports tx_gt_locked_led]

### Any other constraints can be added here

#set_property PACKAGE_PIN AV33 [get_ports init_clk]
set_property PACKAGE_PIN BD23 [get_ports sys_reset]
set_property PACKAGE_PIN BF22 [get_ports send_continuous_pkts]
set_property PACKAGE_PIN BE22 [get_ports simplex_mode_rx_aligned]
set_property PACKAGE_PIN BB24 [get_ports lbus_tx_rx_restart_in]
#set_property PACKAGE_PIN U9 [get_ports gt_ref_clk_p]

set_property PACKAGE_PIN AV34 [get_ports tx_busy_led]
set_property PACKAGE_PIN AY30 [get_ports tx_done_led]
set_property PACKAGE_PIN BB32 [get_ports tx_gt_locked_led]

set_property PACKAGE_PIN AY23 [get_ports init_clk_n]
set_property PACKAGE_PIN AY24 [get_ports init_clk_p]
#set_property PACKAGE_PIN W9 [get_ports gt_ref_clk_p]

set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports init_clk_n]
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports init_clk_p]

set_property PACKAGE_PIN AB38 [get_ports gt_ref_clk_p]