module cau1_2_tb();
reg clk,en,clear;
wire[3:0] q;
cau1_2 ins(
.en   (en),
.clk  (clk),
.clear(clear),
.q    (q)
);

always begin
 #10000 clk = ~clk;
end
initial begin
  $display("\ttime\tclk\ten\tclear\tq");
  $monitor("%d\t%d\t%d\t%d\t%d", $time,clk,en,clear,q);
  en = 0;
  clk = 1;
  clear = 0;
  #10000 clear = 1;
  #20000 en = 1;
end
endmodule