LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity fsm3 is
	port(clock, w, reset : in std_logic;
					       z : out std_logic;
		            state : out std_logic_vector(8 downto 0)); --input output ports

	end fsm;

	architecture behavior of fsm is

		type State_type is (A,B,C,D,E,F,G,H,I);
		signal y_Q, Y_D : State_type;

		begin
			process(w, y_Q)--state table
			begin
					case y_Q is
						when A
							state<="000000001";
							z<= '0';
							if(w = '0') then
								y_Q <=B;--if we get a 0, go to B
							else
								y_Q <=F;--if we get a 1 go to F
							end if;

						when B
							state<="000000010";
							z<= '0';
							if(w = '0') then
								y_Q <=C;
							else
								y_Q <=F;
							end if;

						when C
							state<="000000100";
							z<= '0';
							if(w = '0') then
								y_Q <=D;
							else
								y_Q <=F;
							end if;

						when D
							state<="000001000";
							z<= '0';
							if(w = '0') then
								y_Q <=E;
							else
								y_Q <=F;
							end if;

						when E
							state<="000010000";
							z<='1';
							if(w = '0') then
								y_Q <=E;
							else
								y_Q <=F;
							end if;

						when F
							state<="000100000";
							z<='0';
							if(w = '1') then
								y_Q <=G;--if we get a 1, go to G
							else
								y_Q <=B;--if we get a 0, go to B
							end if;

						when G
							state<="001000000";
							z<='0';
							if(w = '1') then
								y_Q <=H;
							else
								y_Q <=B;
							end if;

						when H
							state<="010000000";
							z<='0';
							if(w = '1') then
								y_Q <=I;
							else
								y_Q <=B;
							end if;

						when I
							state<="100000000";
							z<='1';
							if(w = '1') then
								y_Q <=I;
							else
								y_Q <=B;
							end if;

					end case;
			end process;--state table

			process(clock)
			begin
				if(clock'event and clock = '1') then

			end process;

			--assignments for output z and LEDs







end behavior;