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- module zad4(
- input CLOCK_50,
- output [0:6] HEX0, HEX1, HEX2, HEX3);
- turn_word(CLOCK_50, HEX0, HEX1,HEX2,HEX3);
- endmodule
- module turn_word(
- input clk,
- output [0:6] h0, h1, h2, h3);
- wire left, right;
- assign left=1;
- assign right=0;
- reg [1:0] combination;
- wire clockTact;
- display_word(combination,h0,h1,h2,h3);
- counter_to_make_delay(clk,1,clockTact);
- always@(posedge clockTact)
- begin
- if(left==1)
- begin
- if(combination==2'b00)
- combination<=3;
- else
- combination<=combination-1;
- end
- if(right==1)
- begin
- if(combination==2'b11)
- combination<=0;
- else
- combination<=combination+1;
- end
- end
- endmodule
- module counter_to_make_delay(
- input clk, aclr,
- output reg clockTact);
- reg [25:0] i;
- always@(posedge clk, negedge aclr)
- if(!aclr)
- begin
- i<=0;
- clockTact<=0;
- end
- else
- begin
- if(i==3)
- begin
- i<=0;
- clockTact<=1;
- end
- else
- begin
- i<=i+1;
- clockTact<=0;
- end
- end
- endmodule
- module display_word(
- input [1:0] combination,
- output [0:6] h0, h1, h2, h3);
- reg [1:0] char0 = 2'b00; //spacja
- reg [1:0] char1 = 2'b01; // 1
- reg [1:0] char2 = 2'b10; // E
- reg [1:0] char3 = 2'b11; // d
- decoder_hex(char0,h0);
- decoder_hex(char1,h1);
- decoder_hex(char2,h2);
- decoder_hex(char3,h3);
- always@(*)
- case(combination)
- 2'b00:
- begin
- char0<=2'b00;
- char1<=2'b01;
- char2<=2'b10;
- char3<=2'b11;
- end
- 2'b01:
- begin
- char0<=2'b01;
- char1<=2'b10;
- char2<=2'b11;
- char3<=2'b00;
- end
- 2'b10:
- begin
- char0<=2'b10;
- char1<=2'b11;
- char2<=2'b00;
- char3<=2'b01;
- end
- 2'b11:
- begin
- char0<=2'b11;
- char1<=2'b00;
- char2<=2'b01;
- char3<=2'b10;
- end
- endcase
- endmodule
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