1mfbenq

module SPI_SLAVE
(
	input			clock,		// 50 MHz
	input			reset_n,

	output	reg		RX_valid,	// data valid pulse
	output	reg	[7:0]	RX_data,	// mosi byte

	input			TX_valid,	// data valid (obtain miso byte ; held until TX_received is set)
	output			TX_request,	// request next byte (pulse to prepare next miso byte)
	output	reg		TX_received,	// acknowledge (flag that miso has been received)
	input		[7:0]	TX_data,	// miso byte

	input			SPI_clock,
	output			SPI_miso,
	input			SPI_mosi,
	input			SPI_cs_n
);
	/* mosi omitted for brevity */

	reg	[7:0]	TX_preload;	// local miso byte copy
	reg	[2:0]	TX_counter;	// miso bit counter (7 .. 0)
	reg	[2:0]	sync0_TX_counter, sync1_TX_counter; // sync miso counter to sys clock
	reg		TX_done, prev_TX_done;	// used to pulse TX_request

	// TX_request process
	assign	TX_request = TX_done & ~prev_TX_done;
	always @(posedge clock)
	begin
		prev_TX_done <= TX_done;
		sync0_TX_counter <= TX_counter;
		sync1_TX_counter <= sync0_TX_counter;

		if (sync1_TX_counter == 3'd6)
			TX_done <= 1'b1;
		else
			TX_done <= 1'b0;
	end

	reg	[8:0]	TX_temp; // used to shift out miso bits

	// process to load/shift TX_temp
	always @(negedge SPI_clock)
	begin
		// shift and load
		if (TX_counter == 3'd1)			  // using 8'ha5 constant for debugging
			TX_temp <= { TX_temp[7], 8'h5A }; // TX_preload };
		// shift
		else
			TX_temp <= TX_temp << 1'b1;
	end

	// TX_preload and TX_received process
	always @(posedge clock, negedge reset_n)
	begin
		if (!reset_n)
		begin
			TX_preload <= 8'd0;
			TX_received <= 1'b0;
		end else if (TX_valid)	// grab TX_data and set TX_received pulse
		begin
			TX_preload <= TX_data;
			TX_received <= 1'b1;
		end else		// end TX_received pulse
			TX_received <= 1'b0;
	end

	// TX_counter process
	always @(negedge SPI_clock, posedge SPI_cs_n)
	begin	if (SPI_cs_n)
			TX_counter <= 3'd7;
		else
			TX_counter <= TX_counter - 3'd1;
	end

	// miso is simply the high bit of the shift reg
	assign	SPI_miso = TX_temp[8];

endmodule