Advertisement
Guest User

Untitled

a guest
Oct 16th, 2017
68
0
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 4.67 KB | None | 0 0
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.STD_LOGIC_ARITH.ALL;
  4. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  5. use IEEE.numeric_std.all;
  6.  
  7. entity cw6 is
  8. port (
  9. clk_i : in std_logic;
  10. led7_seg_o : out std_logic_vector(7 downto 0) := "11111111";
  11. led7_an_o : out std_logic_vector(3 downto 0) := "1111";
  12. sw_i : in std_logic_vector(7 downto 0) := "00000000";
  13. btn_i : in std_logic_vector(3 downto 0) := "0000"
  14. );
  15. end cw6;
  16.  
  17. architecture Behavioral of cw6 is
  18. signal an0 : std_logic_vector(7 downto 0);
  19. signal an1 : std_logic_vector(7 downto 0);
  20. signal an2 : std_logic_vector(7 downto 0);
  21. signal an3 : std_logic_vector(7 downto 0);
  22.  
  23. component wyswietlacz is
  24. port (
  25. clk_i : in std_logic;
  26. led7_seg_o : out std_logic_vector(7 downto 0):= "11111111";
  27. led7_an_o : out std_logic_vector(3 downto 0):= "1111";
  28. an0 : in std_logic_vector(7 downto 0) := "11111111";
  29. an1 : in std_logic_vector(7 downto 0) := "11111111";
  30. an2 : in std_logic_vector(7 downto 0) := "11111111";
  31. an3 : in std_logic_vector(7 downto 0) := "11111111"
  32. );
  33. end component;
  34.  
  35. component zad6 is
  36. port (
  37. clk_i : in std_logic;
  38. an0 : out std_logic_vector(7 downto 0);
  39. an1 : out std_logic_vector(7 downto 0);
  40. an2 : out std_logic_vector(7 downto 0);
  41. an3 : out std_logic_vector(7 downto 0);
  42. sw_i : in std_logic_vector(7 downto 0) := "00000000";
  43. btn_i : in std_logic_vector(3 downto 0) := "0000"
  44. );
  45. end component;
  46.  
  47. begin
  48. wysw: wyswietlacz
  49. port map(
  50. clk_i => clk_i,
  51. led7_seg_o => led7_seg_o,
  52. led7_an_o =>led7_an_o,
  53. an0 => an0,
  54. an1 => an1,
  55. an2 => an2,
  56. an3 => an3
  57. );
  58.  
  59. wysw1: zad6
  60. port map(
  61. clk_i => clk_i,
  62. an0 => an0,
  63. an1 => an1,
  64. an2 => an2,
  65. an3 => an3,
  66. sw_i => sw_i,
  67. btn_i => btn_i
  68. );
  69.  
  70. end Behavioral;
  71.  
  72.  
  73. library IEEE;
  74. use IEEE.STD_LOGIC_1164.ALL;
  75. use IEEE.STD_LOGIC_ARITH.ALL;
  76. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  77. use IEEE.numeric_std.all;
  78.  
  79. entity wyswietlacz is
  80. port (
  81. clk_i : in std_logic;
  82. led7_seg_o : out std_logic_vector(7 downto 0):= "11111111";
  83. led7_an_o : out std_logic_vector(3 downto 0):= "1111";
  84. an0 : in std_logic_vector(7 downto 0) := "11111111";
  85. an1 : in std_logic_vector(7 downto 0) := "11111111";
  86. an2 : in std_logic_vector(7 downto 0) := "11111111";
  87. an3 : in std_logic_vector(7 downto 0) := "11111111"
  88. );
  89. end wyswietlacz;
  90.  
  91. architecture Behavioral of wyswietlacz is
  92. signal i: integer :=0;
  93.  
  94. begin
  95. lcd: process (clk_i) is
  96. begin
  97. if rising_edge (clk_i) then
  98. i<=i+1;
  99. if i=1 then
  100. led7_an_o <= "0111";
  101. led7_seg_o <= an3;
  102. elsif i=100 then
  103. led7_an_o <= "1011";
  104. led7_seg_o <= an2;
  105. elsif i=200 then
  106. led7_an_o <= "1101";
  107. led7_seg_o <= an1;
  108. elsif i=300 then
  109. led7_an_o <= "1110";
  110. led7_seg_o <= an0;
  111. elsif i=400 then
  112. i<=0;
  113. end if;
  114. end if;
  115. end process lcd;
  116. end Behavioral;
  117.  
  118.  
  119. library IEEE;
  120. use IEEE.STD_LOGIC_1164.ALL;
  121. use IEEE.STD_LOGIC_ARITH.ALL;
  122. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  123. use IEEE.numeric_std.all;
  124.  
  125. entity zad6 is
  126. port (
  127. clk_i : in std_logic;
  128. an0 : out std_logic_vector(7 downto 0);
  129. an1 : out std_logic_vector(7 downto 0);
  130. an2 : out std_logic_vector(7 downto 0);
  131. an3 : out std_logic_vector(7 downto 0);
  132. sw_i : in std_logic_vector(7 downto 0);
  133. btn_i : in std_logic_vector(3 downto 0)
  134. );
  135. end zad6;
  136.  
  137. architecture Behavioral of zad6 is
  138. signal cyfra : std_logic_vector(3 downto 0);
  139. signal ledbuf : std_logic_vector(6 downto 0);
  140.  
  141. begin
  142. liczba: process (clk_i) is
  143. begin
  144. --KROPKA
  145. if rising_edge (clk_i) then
  146. an3(0) <= not sw_i(7);
  147. an2(0) <= not sw_i(6);
  148. an1(0) <= not sw_i(5);
  149. an0(0) <= not sw_i(4);
  150.  
  151. cyfra <= sw_i (3 downto 0);
  152. case CONV_INTEGER (cyfra) is
  153. when 0 => ledbuf <= "0000001";
  154. when 1 => ledbuf <= "1001111";
  155. when 2 => ledbuf <= "0010010";
  156. when 3 => ledbuf <= "0000110";
  157. when 4 => ledbuf <= "1001100";
  158. when 5 => ledbuf <= "0100100";
  159. when 6 => ledbuf <= "0100000";
  160. when 7 => ledbuf <= "0001111";
  161. when 8 => ledbuf <= "0000000";
  162. when 9 => ledbuf <= "0000100";
  163. when 10 => ledbuf <= "0001000";
  164. when 11 => ledbuf <= "0000000";
  165. when 12 => ledbuf <= "0110001";
  166. when 13 => ledbuf <= "0000001";
  167. when 14 => ledbuf <= "0110000";
  168. when others => ledbuf <= "0111000";
  169. end case;
  170.  
  171. if btn_i(3)='1' then
  172. an3(7 downto 1) <= ledbuf;
  173. elsif btn_i(2)='1' then
  174. an2(7 downto 1) <= ledbuf;
  175. elsif btn_i(1)='1' then
  176. an1(7 downto 1) <= ledbuf;
  177. elsif btn_i(0)='1' then
  178. an0(7 downto 1) <= ledbuf;
  179. end if;
  180.  
  181. end if;
  182. end process liczba;
  183. end Behavioral;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement