1-10Hz

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;

entity liczniknew is
port (in_clock : in std_logic:='0';
		out10h : buffer std_logic:='0';
		out1h : buffer std_logic:='0');
end liczniknew;
architecture dzielnik of liczniknew is
signal count1: integer:=5000000;
signal count2: integer:=50000000;
begin
process(in_clock)
begin
if rising_edge(in_clock) then
count1<=count1-1;
count2<=count2-1;
if count1 =0  then--10Hz
out10h<=not out10h;
if count2 = 0 then--1Hz
out1h<=not out1h;
count1<=5000000;
count2<=50000000;
end if;
end if;
end if;
end process;
end dzielnik;