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1-10Hz

a guest Jan 22nd, 2020 68 Never
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  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.all;
  3. use ieee.std_logic_unsigned.all;
  4.  
  5. entity liczniknew is
  6. port (in_clock : in std_logic:='0';
  7.         out10h : buffer std_logic:='0';
  8.         out1h : buffer std_logic:='0');
  9. end liczniknew;
  10. architecture dzielnik of liczniknew is
  11. signal count1: integer:=5000000;
  12. signal count2: integer:=50000000;
  13. begin
  14. process(in_clock)
  15. begin
  16. if rising_edge(in_clock) then
  17. count1<=count1-1;
  18. count2<=count2-1;
  19. if count1 =0  then--10Hz
  20. out10h<=not out10h;
  21. if count2 = 0 then--1Hz
  22. out1h<=not out1h;
  23. count1<=5000000;
  24. count2<=50000000;
  25. end if;
  26. end if;
  27. end if;
  28. end process;
  29. end dzielnik;
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