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  1. [1m[NOTE ] coreboot-24.05-263-gbbac6b9f8a80 Sat Jun 15 11:48:04 UTC 2024 x86_32 bootblock starting (log level: 7)...
  2. [DEBUG] CPU: Intel(R) Xeon(R) CPU E3-1270 v6 @ 3.80GHz
  3. [DEBUG] CPU: ID 906e9, Kabylake H B0, ucode: 000000f7
  4. [DEBUG] CPU: AES supported, TXT supported, VT supported
  5. [DEBUG] MCH: device id 5918 (rev 05) is Kabylake DT 2
  6. [DEBUG] PCH: device id a149 (rev 31) is C236
  7. [DEBUG] IGD: device id ffff (rev ff) is Unknown
  8. [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x510000.
  9. [DEBUG] FMAP: base = 0xff000000 size = 0x1000000 #areas = 6
  10. [DEBUG] FMAP: area COREBOOT found @ 510200 (11468288 bytes)
  11. [INFO ] CBFS: mcache u/0xfef04e00 built for 19 files, used 0x400 of 0x4000 bytes
  12. [INFO ] CBFS: Found 'fallback/romstage' u/0x80 size 0xc8b0 in mcache u/0xfef04e2c
  13. [DEBUG] BS: bootblock times (exec / console): total (unknown) / 77 ms
  14. 
  15. 
  16. [NOTE ] coreboot-24.05-263-gbbac6b9f8a80 Sat Jun 15 11:48:04 UTC 2024 x86_32 romstage starting (log level: 7)...
  17. [INFO ] POST: 0x00
  18. [DEBUG] pm1_sts: 0000 pm1_en: 0000 pm1_cnt: 00000000
  19. [DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
  20. [DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
  21. [DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
  22. [DEBUG] gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000
  23. [DEBUG] TCO_STS: 0000 0000
  24. [DEBUG] GEN_PMCON: a0040200 00004006
  25. [DEBUG] GBLRST_CAUSE: 00000000 00000000
  26. [DEBUG] prev_sleep_state 5 (S5)
  27. [DEBUG] FMAP: area COREBOOT found @ 510200 (11468288 bytes)
  28. [INFO ] CBFS: Found 'fspm.bin' u/0x6adc0 size 0x63000 in mcache u/0xfef050b0
  29. [INFO ] POST: 0x34
  30. [DEBUG] FMAP: area RW_MRC_CACHE found @ 500000 (65536 bytes)
  31. [NOTE ] MRC: no data in 'RW_MRC_CACHE'
  32. [INFO ] POST: 0x36
  33. [INFO ] POST: 0x92
  34. [INFO ] POST: 0x98
  35. [DEBUG] CBMEM:
  36. [DEBUG] IMD: root @ 0x7f7ff000 254 entries.
  37. [DEBUG] IMD: root @ 0x7f7fec00 62 entries.
  38. [DEBUG] FMAP: area RW_MRC_CACHE found @ 500000 (65536 bytes)
  39. [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
  40. [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
  41. [NOTE ] MRC: no data in 'RW_MRC_CACHE'
  42. [DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update.
  43. [DEBUG] MRC: updated 'RW_MRC_CACHE'.
  44. [DEBUG] 4 DIMMs found
  45. [DEBUG] SMM Memory Map
  46. [DEBUG] SMRAM : 0x7f800000 0x800000
  47. [DEBUG] Subregion 0: 0x7f800000 0x200000
  48. [DEBUG] Subregion 1: 0x7fa00000 0x200000
  49. [DEBUG] Subregion 2: 0x7fc00000 0x400000
  50. [DEBUG] top_of_ram = 0x7f800000
  51. [INFO ] CBFS: Found 'fallback/postcar' u/0xf1e40 size 0x5408 in mcache u/0xfef05124
  52. [DEBUG] Loading module at 0x7f3cf000 with entry 0x7f3cf031. filesize: 0x5108 memsize: 0xb430
  53. [DEBUG] Processing 176 relocs. Offset value of 0x7d3cf000
  54. [DEBUG] BS: romstage times (exec / console): total (unknown) / 182 ms
  55. 
  56. 
  57. [NOTE ] coreboot-24.05-263-gbbac6b9f8a80 Sat Jun 15 11:48:04 UTC 2024 x86_32 postcar starting (log level: 7)...
  58. [DEBUG] FMAP: area COREBOOT found @ 510200 (11468288 bytes)
  59. [INFO ] CBFS: Found 'fallback/ramstage' u/0x41f00 size 0x1d261 in mcache u/0x7f3dd10c
  60. [DEBUG] Loading module at 0x7f282000 with entry 0x7f282000. filesize: 0x3cb60 memsize: 0x14b7f0
  61. [DEBUG] Processing 4362 relocs. Offset value of 0x7b282000
  62. [DEBUG] BS: postcar times (exec / console): total (unknown) / 41 ms
  63. 
  64. 
  65. [NOTE ] coreboot-24.05-263-gbbac6b9f8a80 Sat Jun 15 11:48:04 UTC 2024 x86_32 ramstage starting (log level: 7)...
  66. [INFO ] POST: 0x39
  67. [INFO ] POST: 0x6f
  68. [INFO ] POST: 0x70
  69. [DEBUG] BS: BS_PRE_DEVICE run times (exec / console): 0 / 3 ms
  70. [DEBUG] microcode: sig=0x906e9 pf=0x2 revision=0xf7
  71. [DEBUG] FMAP: area COREBOOT found @ 510200 (11468288 bytes)
  72. [INFO ] CBFS: Found 'cpu_microcode_blob.bin' u/0xc9c0 size 0x35400 in mcache u/0x7f3dd0ac
  73. [DEBUG] Skip microcode update
  74. [INFO ] CBFS: Found 'fsps.bin' u/0xcde00 size 0x23ff2 in mcache u/0x7f3dd2f0
  75. [DEBUG] Detected 4 core, 8 thread CPU.
  76. [DEBUG] Setting up SMI for CPU
  77. [DEBUG] IED base = 0x7fc00000
  78. [DEBUG] IED size = 0x00400000
  79. [INFO ] Will perform SMM setup.
  80. [INFO ] CPU: Intel(R) Xeon(R) CPU E3-1270 v6 @ 3.80GHz.
  81. [INFO ] LAPIC 0x0 in XAPIC mode.
  82. [DEBUG] CPU: APIC: 00 enabled
  83. [DEBUG] CPU: APIC: 01 enabled
  84. [DEBUG] CPU: APIC: 02 enabled
  85. [DEBUG] CPU: APIC: 03 enabled
  86. [DEBUG] CPU: APIC: 04 enabled
  87. [DEBUG] CPU: APIC: 05 enabled
  88. [DEBUG] CPU: APIC: 06 enabled
  89. [DEBUG] CPU: APIC: 07 enabled
  90. [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
  91. [DEBUG] Processing 16 relocs. Offset value of 0x00030000
  92. [DEBUG] Attempting to start 7 APs
  93. [DEBUG] Waiting for 10ms after sending INIT.
  94. [DEBUG] Waiting for SIPI to complete...
  95. [DEBUG] done.
  96. [INFO ] LAPIC 0x1 in XAPIC mode.
  97. [INFO ] LAPIC 0x6 in XAPIC mode.
  98. [INFO ] LAPIC 0x7 in XAPIC mode.
  99. [INFO ] AP: slot 5 apic_id 6, MCU rev: 0x000000f7
  100. [INFO ] AP: slot 4 apic_id 7, MCU rev: 0x000000f7
  101. [INFO ] LAPIC 0x3 in XAPIC mode.
  102. [INFO ] LAPIC 0x2 in XAPIC mode.
  103. [INFO ] AP: slot 6 apic_id 3, MCU rev: 0x000000f7
  104. [INFO ] AP: slot 7 apic_id 2, MCU rev: 0x000000f7
  105. [DEBUG] Waiting for SIPI to complete...
  106. [DEBUG] done.
  107. [INFO ] AP: slot 1 apic_id 1, MCU rev: 0x000000f7
  108. [INFO ] LAPIC 0x4 in XAPIC mode.
  109. [INFO ] LAPIC 0x5 in XAPIC mode.
  110. [INFO ] AP: slot 3 apic_id 4, MCU rev: 0x000000f7
  111. [INFO ] AP: slot 2 apic_id 5, MCU rev: 0x000000f7
  112. [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0
  113. [DEBUG] Processing 9 relocs. Offset value of 0x00038000
  114. [DEBUG] smm_module_setup_stub: stack_top = 0x7f804000
  115. [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
  116. [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
  117. [DEBUG] SMM Module: stub loaded at 38000. Will call 0x7f29ff4d
  118. [DEBUG] Installing permanent SMM handler to 0x7f800000
  119. [DEBUG] HANDLER [0x7f9ff000-0x7f9ffda0]
  120. 
  121. [DEBUG] CPU 0
  122. [DEBUG] ss0 [0x7f9fec00-0x7f9ff000]
  123. [DEBUG] stub0 [0x7f9f7000-0x7f9f71a0]
  124. 
  125. [DEBUG] CPU 1
  126. [DEBUG] ss1 [0x7f9fe800-0x7f9fec00]
  127. [DEBUG] stub1 [0x7f9f6c00-0x7f9f6da0]
  128. 
  129. [DEBUG] CPU 2
  130. [DEBUG] ss2 [0x7f9fe400-0x7f9fe800]
  131. [DEBUG] stub2 [0x7f9f6800-0x7f9f69a0]
  132. 
  133. [DEBUG] CPU 3
  134. [DEBUG] ss3 [0x7f9fe000-0x7f9fe400]
  135. [DEBUG] stub3 [0x7f9f6400-0x7f9f65a0]
  136. 
  137. [DEBUG] CPU 4
  138. [DEBUG] ss4 [0x7f9fdc00-0x7f9fe000]
  139. [DEBUG] stub4 [0x7f9f6000-0x7f9f61a0]
  140. 
  141. [DEBUG] CPU 5
  142. [DEBUG] ss5 [0x7f9fd800-0x7f9fdc00]
  143. [DEBUG] stub5 [0x7f9f5c00-0x7f9f5da0]
  144. 
  145. [DEBUG] CPU 6
  146. [DEBUG] ss6 [0x7f9fd400-0x7f9fd800]
  147. [DEBUG] stub6 [0x7f9f5800-0x7f9f59a0]
  148. 
  149. [DEBUG] CPU 7
  150. [DEBUG] ss7 [0x7f9fd000-0x7f9fd400]
  151. [DEBUG] stub7 [0x7f9f5400-0x7f9f55a0]
  152. 
  153. [DEBUG] stacks [0x7f800000-0x7f804000]
  154. [DEBUG] Loading module at 0x7f9ff000 with entry 0x7f9ff079. filesize: 0xd90 memsize: 0xda0
  155. [DEBUG] Processing 81 relocs. Offset value of 0x7f9ff000
  156. [DEBUG] Loading module at 0x7f9f7000 with entry 0x7f9f7000. filesize: 0x1a0 memsize: 0x1a0
  157. [DEBUG] Processing 9 relocs. Offset value of 0x7f9f7000
  158. [DEBUG] smm_module_setup_stub: stack_top = 0x7f804000
  159. [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
  160. [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x200000
  161. [DEBUG] SMM Module: placing smm entry code at 7f9f6c00, cpu # 0x1
  162. [DEBUG] SMM Module: placing smm entry code at 7f9f6800, cpu # 0x2
  163. [DEBUG] SMM Module: placing smm entry code at 7f9f6400, cpu # 0x3
  164. [DEBUG] SMM Module: placing smm entry code at 7f9f6000, cpu # 0x4
  165. [DEBUG] SMM Module: placing smm entry code at 7f9f5c00, cpu # 0x5
  166. [DEBUG] SMM Module: placing smm entry code at 7f9f5800, cpu # 0x6
  167. [DEBUG] SMM Module: placing smm entry code at 7f9f5400, cpu # 0x7
  168. [DEBUG] SMM Module: stub loaded at 7f9f7000. Will call 0x7f9ff079
  169. [DEBUG] Clearing SMI status registers
  170. [DEBUG] SMI_STS: PM1 
  171. [DEBUG] PM1_STS: TMROF 
  172. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9ef000, cpu = 0
  173. [DEBUG] In relocation handler: CPU 0
  174. [DEBUG] New SMBASE=0x7f9ef000 IEDBASE=0x7fc00000
  175. [DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800
  176. [DEBUG] Relocation complete.
  177. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9ee400, cpu = 3
  178. [DEBUG] In relocation handler: CPU 3
  179. [DEBUG] New SMBASE=0x7f9ee400 IEDBASE=0x7fc00000
  180. [DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800
  181. [DEBUG] Relocation complete.
  182. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9ee800, cpu = 2
  183. [DEBUG] In relocation handler: CPU 2
  184. [DEBUG] New SMBASE=0x7f9ee800 IEDBASE=0x7fc00000
  185. [DEBUG] Relocation complete.
  186. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9eec00, cpu = 1
  187. [DEBUG] In relocation handler: CPU 1
  188. [DEBUG] New SMBASE=0x7f9eec00 IEDBASE=0x7fc00000
  189. [DEBUG] Relocation complete.
  190. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9ee000, cpu = 4
  191. [DEBUG] In relocation handler: CPU 4
  192. [DEBUG] New SMBASE=0x7f9ee000 IEDBASE=0x7fc00000
  193. [DEBUG] Relocation complete.
  194. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9edc00, cpu = 5
  195. [DEBUG] In relocation handler: CPU 5
  196. [DEBUG] New SMBASE=0x7f9edc00 IEDBASE=0x7fc00000
  197. [DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800
  198. [DEBUG] Relocation complete.
  199. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9ed800, cpu = 6
  200. [DEBUG] In relocation handler: CPU 6
  201. [DEBUG] New SMBASE=0x7f9ed800 IEDBASE=0x7fc00000
  202. [DEBUG] Relocation complete.
  203. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9ed400, cpu = 7
  204. [DEBUG] In relocation handler: CPU 7
  205. [DEBUG] New SMBASE=0x7f9ed400 IEDBASE=0x7fc00000
  206. [DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800
  207. [DEBUG] Relocation complete.
  208. [INFO ] Initializing CPU #0
  209. [DEBUG] CPU: vendor Intel device 906e9
  210. [DEBUG] CPU: family 06, model 9e, stepping 09
  211. [DEBUG] Clearing out pending MCEs
  212. [DEBUG] cpu: energy policy set to 6
  213. [INFO ] Turbo is available but hidden
  214. [INFO ] Turbo is available and visible
  215. [DEBUG] Skip microcode update
  216. [INFO ] CPU #0 initialized
  217. [INFO ] Initializing CPU #1
  218. [INFO ] Initializing CPU #2
  219. [INFO ] Initializing CPU #3
  220. [DEBUG] CPU: vendor Intel device 906e9
  221. [DEBUG] CPU: family 06, model 9e, stepping 09
  222. [DEBUG] CPU: vendor Intel device 906e9
  223. [DEBUG] CPU: family 06, model 9e, stepping 09
  224. [DEBUG] Clearing out pending MCEs
  225. [DEBUG] Clearing out pending MCEs
  226. [DEBUG] cpu: energy policy set to 6
  227. [DEBUG] cpu: energy policy set to 6
  228. [DEBUG] Skip microcode update
  229. [INFO ] CPU #2 initialized
  230. [DEBUG] Skip microcode update
  231. [INFO ] CPU #3 initialized
  232. [INFO ] Initializing CPU #4
  233. [INFO ] Initializing CPU #5
  234. [DEBUG] CPU: vendor Intel device 906e9
  235. [DEBUG] CPU: family 06, model 9e, stepping 09
  236. [INFO ] Initializing CPU #6
  237. [INFO ] Initializing CPU #7
  238. [DEBUG] CPU: vendor Intel device 906e9
  239. [DEBUG] CPU: family 06, model 9e, stepping 09
  240. [DEBUG] CPU: vendor Intel device 906e9
  241. [DEBUG] CPU: family 06, model 9e, stepping 09
  242. [DEBUG] Clearing out pending MCEs
  243. [DEBUG] Clearing out pending MCEs
  244. [DEBUG] cpu: energy policy set to 6
  245. [DEBUG] cpu: energy policy set to 6
  246. [DEBUG] Skip microcode update
  247. [INFO ] CPU #6 initialized
  248. [DEBUG] Skip microcode update
  249. [INFO ] CPU #7 initialized
  250. [DEBUG] Clearing out pending MCEs
  251. [DEBUG] CPU: vendor Intel device 906e9
  252. [DEBUG] CPU: family 06, model 9e, stepping 09
  253. [DEBUG] CPU: vendor Intel device 906e9
  254. [DEBUG] CPU: family 06, model 9e, stepping 09
  255. [DEBUG] Clearing out pending MCEs
  256. [DEBUG] Clearing out pending MCEs
  257. [DEBUG] cpu: energy policy set to 6
  258. [DEBUG] cpu: energy policy set to 6
  259. [DEBUG] Skip microcode update
  260. [INFO ] CPU #4 initialized
  261. [DEBUG] Skip microcode update
  262. [INFO ] CPU #5 initialized
  263. [DEBUG] cpu: energy policy set to 6
  264. [DEBUG] Skip microcode update
  265. [INFO ] CPU #1 initialized
  266. [INFO ] bsp_do_flight_plan done after 691 msecs.
  267. [DEBUG] CPU: frequency set to 4200 MHz
  268. [DEBUG] Enabling SMIs.
  269. [DEBUG] Locking SMM.
  270. [DEBUG] VMX status: enabled
  271. [DEBUG] VMX status: enabled
  272. [DEBUG] IA32_FEATURE_CONTROL status: locked
  273. [DEBUG] VMX status: enabled
  274. [DEBUG] VMX status: enabled
  275. [DEBUG] IA32_FEATURE_CONTROL status: locked
  276. [DEBUG] IA32_FEATURE_CONTROL status: locked
  277. [DEBUG] VMX status: enabled
  278. [DEBUG] VMX status: enabled
  279. [DEBUG] IA32_FEATURE_CONTROL status: locked
  280. [DEBUG] IA32_FEATURE_CONTROL status: locked
  281. [DEBUG] VMX status: enabled
  282. [DEBUG] VMX status: enabled
  283. [DEBUG] IA32_FEATURE_CONTROL status: locked
  284. [DEBUG] IA32_FEATURE_CONTROL status: locked
  285. [DEBUG] BS: BS_DEV_INIT_CHIPS entry times (exec / console): 532 / 465 ms
  286. [DEBUG] IA32_FEATURE_CONTROL status: locked
  287. [INFO ] POST: 0x71
  288. [DEBUG] WEAK: src/soc/intel/skylake/chip.c/mainboard_silicon_init_params called
  289. [INFO ] POST: 0x93
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