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- [1m[NOTE ] coreboot-24.05-263-gbbac6b9f8a80 Sat Jun 15 11:48:04 UTC 2024 x86_32 bootblock starting (log level: 7)...[0m
- [0m[DEBUG] CPU: Intel(R) Xeon(R) CPU E3-1270 v6 @ 3.80GHz[0m
- [0m[DEBUG] CPU: ID 906e9, Kabylake H B0, ucode: 000000f7[0m
- [0m[DEBUG] CPU: AES supported, TXT supported, VT supported[0m
- [0m[DEBUG] MCH: device id 5918 (rev 05) is Kabylake DT 2[0m
- [0m[DEBUG] PCH: device id a149 (rev 31) is C236[0m
- [0m[DEBUG] IGD: device id ffff (rev ff) is Unknown[0m
- [0m[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x510000.[0m
- [0m[DEBUG] FMAP: base = 0xff000000 size = 0x1000000 #areas = 6[0m
- [0m[DEBUG] FMAP: area COREBOOT found @ 510200 (11468288 bytes)[0m
- [0m[INFO ] CBFS: mcache u/0xfef04e00 built for 19 files, used 0x400 of 0x4000 bytes[0m
- [0m[INFO ] CBFS: Found 'fallback/romstage' u/0x80 size 0xc8b0 in mcache u/0xfef04e2c[0m
- [0m[DEBUG] BS: bootblock times (exec / console): total (unknown) / 77 ms[0m
- [0m
- [0m
- [1m[NOTE ] coreboot-24.05-263-gbbac6b9f8a80 Sat Jun 15 11:48:04 UTC 2024 x86_32 romstage starting (log level: 7)...[0m
- [0m[INFO ] POST: 0x00[0m
- [0m[DEBUG] pm1_sts: 0000 pm1_en: 0000 pm1_cnt: 00000000[0m
- [0m[DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000[0m
- [0m[DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000[0m
- [0m[DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000[0m
- [0m[DEBUG] gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000[0m
- [0m[DEBUG] TCO_STS: 0000 0000[0m
- [0m[DEBUG] GEN_PMCON: a0040200 00004006[0m
- [0m[DEBUG] GBLRST_CAUSE: 00000000 00000000[0m
- [0m[DEBUG] prev_sleep_state 5 (S5)[0m
- [0m[DEBUG] FMAP: area COREBOOT found @ 510200 (11468288 bytes)[0m
- [0m[INFO ] CBFS: Found 'fspm.bin' u/0x6adc0 size 0x63000 in mcache u/0xfef050b0[0m
- [0m[INFO ] POST: 0x34[0m
- [0m[DEBUG] FMAP: area RW_MRC_CACHE found @ 500000 (65536 bytes)[0m
- [1m[NOTE ] MRC: no data in 'RW_MRC_CACHE'[0m
- [0m[INFO ] POST: 0x36[0m
- [0m[INFO ] POST: 0x92[0m
- [0m[INFO ] POST: 0x98[0m
- [0m[DEBUG] CBMEM:[0m
- [0m[DEBUG] IMD: root @ 0x7f7ff000 254 entries.[0m
- [0m[DEBUG] IMD: root @ 0x7f7fec00 62 entries.[0m
- [0m[DEBUG] FMAP: area RW_MRC_CACHE found @ 500000 (65536 bytes)[0m
- [0m[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.[0m
- [0m[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x1000000[0m
- [1m[NOTE ] MRC: no data in 'RW_MRC_CACHE'[0m
- [0m[DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update.[0m
- [0m[DEBUG] MRC: updated 'RW_MRC_CACHE'.[0m
- [0m[DEBUG] 4 DIMMs found[0m
- [0m[DEBUG] SMM Memory Map[0m
- [0m[DEBUG] SMRAM : 0x7f800000 0x800000[0m
- [0m[DEBUG] Subregion 0: 0x7f800000 0x200000[0m
- [0m[DEBUG] Subregion 1: 0x7fa00000 0x200000[0m
- [0m[DEBUG] Subregion 2: 0x7fc00000 0x400000[0m
- [0m[DEBUG] top_of_ram = 0x7f800000[0m
- [0m[INFO ] CBFS: Found 'fallback/postcar' u/0xf1e40 size 0x5408 in mcache u/0xfef05124[0m
- [0m[DEBUG] Loading module at 0x7f3cf000 with entry 0x7f3cf031. filesize: 0x5108 memsize: 0xb430[0m
- [0m[DEBUG] Processing 176 relocs. Offset value of 0x7d3cf000[0m
- [0m[DEBUG] BS: romstage times (exec / console): total (unknown) / 182 ms[0m
- [0m
- [0m
- [1m[NOTE ] coreboot-24.05-263-gbbac6b9f8a80 Sat Jun 15 11:48:04 UTC 2024 x86_32 postcar starting (log level: 7)...[0m
- [0m[DEBUG] FMAP: area COREBOOT found @ 510200 (11468288 bytes)[0m
- [0m[INFO ] CBFS: Found 'fallback/ramstage' u/0x41f00 size 0x1d261 in mcache u/0x7f3dd10c[0m
- [0m[DEBUG] Loading module at 0x7f282000 with entry 0x7f282000. filesize: 0x3cb60 memsize: 0x14b7f0[0m
- [0m[DEBUG] Processing 4362 relocs. Offset value of 0x7b282000[0m
- [0m[DEBUG] BS: postcar times (exec / console): total (unknown) / 41 ms[0m
- [0m
- [0m
- [1m[NOTE ] coreboot-24.05-263-gbbac6b9f8a80 Sat Jun 15 11:48:04 UTC 2024 x86_32 ramstage starting (log level: 7)...[0m
- [0m[INFO ] POST: 0x39[0m
- [0m[INFO ] POST: 0x6f[0m
- [0m[INFO ] POST: 0x70[0m
- [0m[DEBUG] BS: BS_PRE_DEVICE run times (exec / console): 0 / 3 ms[0m
- [0m[DEBUG] microcode: sig=0x906e9 pf=0x2 revision=0xf7[0m
- [0m[DEBUG] FMAP: area COREBOOT found @ 510200 (11468288 bytes)[0m
- [0m[INFO ] CBFS: Found 'cpu_microcode_blob.bin' u/0xc9c0 size 0x35400 in mcache u/0x7f3dd0ac[0m
- [0m[DEBUG] Skip microcode update[0m
- [0m[INFO ] CBFS: Found 'fsps.bin' u/0xcde00 size 0x23ff2 in mcache u/0x7f3dd2f0[0m
- [0m[DEBUG] Detected 4 core, 8 thread CPU.[0m
- [0m[DEBUG] Setting up SMI for CPU[0m
- [0m[DEBUG] IED base = 0x7fc00000[0m
- [0m[DEBUG] IED size = 0x00400000[0m
- [0m[INFO ] Will perform SMM setup.[0m
- [0m[INFO ] CPU: Intel(R) Xeon(R) CPU E3-1270 v6 @ 3.80GHz.[0m
- [0m[INFO ] LAPIC 0x0 in XAPIC mode.[0m
- [0m[DEBUG] CPU: APIC: 00 enabled[0m
- [0m[DEBUG] CPU: APIC: 01 enabled[0m
- [0m[DEBUG] CPU: APIC: 02 enabled[0m
- [0m[DEBUG] CPU: APIC: 03 enabled[0m
- [0m[DEBUG] CPU: APIC: 04 enabled[0m
- [0m[DEBUG] CPU: APIC: 05 enabled[0m
- [0m[DEBUG] CPU: APIC: 06 enabled[0m
- [0m[DEBUG] CPU: APIC: 07 enabled[0m
- [0m[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178[0m
- [0m[DEBUG] Processing 16 relocs. Offset value of 0x00030000[0m
- [0m[DEBUG] Attempting to start 7 APs[0m
- [0m[DEBUG] Waiting for 10ms after sending INIT.[0m
- [0m[DEBUG] Waiting for SIPI to complete...[0m
- [0m[DEBUG] done.[0m
- [0m[INFO ] LAPIC 0x1 in XAPIC mode.[0m
- [0m[INFO ] LAPIC 0x6 in XAPIC mode.[0m
- [0m[INFO ] LAPIC 0x7 in XAPIC mode.[0m
- [0m[INFO ] AP: slot 5 apic_id 6, MCU rev: 0x000000f7[0m
- [0m[INFO ] AP: slot 4 apic_id 7, MCU rev: 0x000000f7[0m
- [0m[INFO ] LAPIC 0x3 in XAPIC mode.[0m
- [0m[INFO ] LAPIC 0x2 in XAPIC mode.[0m
- [0m[INFO ] AP: slot 6 apic_id 3, MCU rev: 0x000000f7[0m
- [0m[INFO ] AP: slot 7 apic_id 2, MCU rev: 0x000000f7[0m
- [0m[DEBUG] Waiting for SIPI to complete...[0m
- [0m[DEBUG] done.[0m
- [0m[INFO ] AP: slot 1 apic_id 1, MCU rev: 0x000000f7[0m
- [0m[INFO ] LAPIC 0x4 in XAPIC mode.[0m
- [0m[INFO ] LAPIC 0x5 in XAPIC mode.[0m
- [0m[INFO ] AP: slot 3 apic_id 4, MCU rev: 0x000000f7[0m
- [0m[INFO ] AP: slot 2 apic_id 5, MCU rev: 0x000000f7[0m
- [0m[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0[0m
- [0m[DEBUG] Processing 9 relocs. Offset value of 0x00038000[0m
- [0m[DEBUG] smm_module_setup_stub: stack_top = 0x7f804000[0m
- [0m[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800[0m
- [0m[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000[0m
- [0m[DEBUG] SMM Module: stub loaded at 38000. Will call 0x7f29ff4d[0m
- [0m[DEBUG] Installing permanent SMM handler to 0x7f800000[0m
- [0m[DEBUG] HANDLER [0x7f9ff000-0x7f9ffda0][0m
- [0m
- [0m[DEBUG] CPU 0[0m
- [0m[DEBUG] ss0 [0x7f9fec00-0x7f9ff000][0m
- [0m[DEBUG] stub0 [0x7f9f7000-0x7f9f71a0][0m
- [0m
- [0m[DEBUG] CPU 1[0m
- [0m[DEBUG] ss1 [0x7f9fe800-0x7f9fec00][0m
- [0m[DEBUG] stub1 [0x7f9f6c00-0x7f9f6da0][0m
- [0m
- [0m[DEBUG] CPU 2[0m
- [0m[DEBUG] ss2 [0x7f9fe400-0x7f9fe800][0m
- [0m[DEBUG] stub2 [0x7f9f6800-0x7f9f69a0][0m
- [0m
- [0m[DEBUG] CPU 3[0m
- [0m[DEBUG] ss3 [0x7f9fe000-0x7f9fe400][0m
- [0m[DEBUG] stub3 [0x7f9f6400-0x7f9f65a0][0m
- [0m
- [0m[DEBUG] CPU 4[0m
- [0m[DEBUG] ss4 [0x7f9fdc00-0x7f9fe000][0m
- [0m[DEBUG] stub4 [0x7f9f6000-0x7f9f61a0][0m
- [0m
- [0m[DEBUG] CPU 5[0m
- [0m[DEBUG] ss5 [0x7f9fd800-0x7f9fdc00][0m
- [0m[DEBUG] stub5 [0x7f9f5c00-0x7f9f5da0][0m
- [0m
- [0m[DEBUG] CPU 6[0m
- [0m[DEBUG] ss6 [0x7f9fd400-0x7f9fd800][0m
- [0m[DEBUG] stub6 [0x7f9f5800-0x7f9f59a0][0m
- [0m
- [0m[DEBUG] CPU 7[0m
- [0m[DEBUG] ss7 [0x7f9fd000-0x7f9fd400][0m
- [0m[DEBUG] stub7 [0x7f9f5400-0x7f9f55a0][0m
- [0m
- [0m[DEBUG] stacks [0x7f800000-0x7f804000][0m
- [0m[DEBUG] Loading module at 0x7f9ff000 with entry 0x7f9ff079. filesize: 0xd90 memsize: 0xda0[0m
- [0m[DEBUG] Processing 81 relocs. Offset value of 0x7f9ff000[0m
- [0m[DEBUG] Loading module at 0x7f9f7000 with entry 0x7f9f7000. filesize: 0x1a0 memsize: 0x1a0[0m
- [0m[DEBUG] Processing 9 relocs. Offset value of 0x7f9f7000[0m
- [0m[DEBUG] smm_module_setup_stub: stack_top = 0x7f804000[0m
- [0m[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800[0m
- [0m[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x200000[0m
- [0m[DEBUG] SMM Module: placing smm entry code at 7f9f6c00, cpu # 0x1[0m
- [0m[DEBUG] SMM Module: placing smm entry code at 7f9f6800, cpu # 0x2[0m
- [0m[DEBUG] SMM Module: placing smm entry code at 7f9f6400, cpu # 0x3[0m
- [0m[DEBUG] SMM Module: placing smm entry code at 7f9f6000, cpu # 0x4[0m
- [0m[DEBUG] SMM Module: placing smm entry code at 7f9f5c00, cpu # 0x5[0m
- [0m[DEBUG] SMM Module: placing smm entry code at 7f9f5800, cpu # 0x6[0m
- [0m[DEBUG] SMM Module: placing smm entry code at 7f9f5400, cpu # 0x7[0m
- [0m[DEBUG] SMM Module: stub loaded at 7f9f7000. Will call 0x7f9ff079[0m
- [0m[DEBUG] Clearing SMI status registers[0m
- [0m[DEBUG] SMI_STS: PM1 [0m
- [0m[DEBUG] PM1_STS: TMROF [0m
- [0m[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9ef000, cpu = 0[0m
- [0m[DEBUG] In relocation handler: CPU 0[0m
- [0m[DEBUG] New SMBASE=0x7f9ef000 IEDBASE=0x7fc00000[0m
- [0m[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800[0m
- [0m[DEBUG] Relocation complete.[0m
- [0m[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9ee400, cpu = 3[0m
- [0m[DEBUG] In relocation handler: CPU 3[0m
- [0m[DEBUG] New SMBASE=0x7f9ee400 IEDBASE=0x7fc00000[0m
- [0m[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800[0m
- [0m[DEBUG] Relocation complete.[0m
- [0m[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9ee800, cpu = 2[0m
- [0m[DEBUG] In relocation handler: CPU 2[0m
- [0m[DEBUG] New SMBASE=0x7f9ee800 IEDBASE=0x7fc00000[0m
- [0m[DEBUG] Relocation complete.[0m
- [0m[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9eec00, cpu = 1[0m
- [0m[DEBUG] In relocation handler: CPU 1[0m
- [0m[DEBUG] New SMBASE=0x7f9eec00 IEDBASE=0x7fc00000[0m
- [0m[DEBUG] Relocation complete.[0m
- [0m[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9ee000, cpu = 4[0m
- [0m[DEBUG] In relocation handler: CPU 4[0m
- [0m[DEBUG] New SMBASE=0x7f9ee000 IEDBASE=0x7fc00000[0m
- [0m[DEBUG] Relocation complete.[0m
- [0m[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9edc00, cpu = 5[0m
- [0m[DEBUG] In relocation handler: CPU 5[0m
- [0m[DEBUG] New SMBASE=0x7f9edc00 IEDBASE=0x7fc00000[0m
- [0m[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800[0m
- [0m[DEBUG] Relocation complete.[0m
- [0m[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9ed800, cpu = 6[0m
- [0m[DEBUG] In relocation handler: CPU 6[0m
- [0m[DEBUG] New SMBASE=0x7f9ed800 IEDBASE=0x7fc00000[0m
- [0m[DEBUG] Relocation complete.[0m
- [0m[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9ed400, cpu = 7[0m
- [0m[DEBUG] In relocation handler: CPU 7[0m
- [0m[DEBUG] New SMBASE=0x7f9ed400 IEDBASE=0x7fc00000[0m
- [0m[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800[0m
- [0m[DEBUG] Relocation complete.[0m
- [0m[INFO ] Initializing CPU #0[0m
- [0m[DEBUG] CPU: vendor Intel device 906e9[0m
- [0m[DEBUG] CPU: family 06, model 9e, stepping 09[0m
- [0m[DEBUG] Clearing out pending MCEs[0m
- [0m[DEBUG] cpu: energy policy set to 6[0m
- [0m[INFO ] Turbo is available but hidden[0m
- [0m[INFO ] Turbo is available and visible[0m
- [0m[DEBUG] Skip microcode update[0m
- [0m[INFO ] CPU #0 initialized[0m
- [0m[INFO ] Initializing CPU #1[0m
- [0m[INFO ] Initializing CPU #2[0m
- [0m[INFO ] Initializing CPU #3[0m
- [0m[DEBUG] CPU: vendor Intel device 906e9[0m
- [0m[DEBUG] CPU: family 06, model 9e, stepping 09[0m
- [0m[DEBUG] CPU: vendor Intel device 906e9[0m
- [0m[DEBUG] CPU: family 06, model 9e, stepping 09[0m
- [0m[DEBUG] Clearing out pending MCEs[0m
- [0m[DEBUG] Clearing out pending MCEs[0m
- [0m[DEBUG] cpu: energy policy set to 6[0m
- [0m[DEBUG] cpu: energy policy set to 6[0m
- [0m[DEBUG] Skip microcode update[0m
- [0m[INFO ] CPU #2 initialized[0m
- [0m[DEBUG] Skip microcode update[0m
- [0m[INFO ] CPU #3 initialized[0m
- [0m[INFO ] Initializing CPU #4[0m
- [0m[INFO ] Initializing CPU #5[0m
- [0m[DEBUG] CPU: vendor Intel device 906e9[0m
- [0m[DEBUG] CPU: family 06, model 9e, stepping 09[0m
- [0m[INFO ] Initializing CPU #6[0m
- [0m[INFO ] Initializing CPU #7[0m
- [0m[DEBUG] CPU: vendor Intel device 906e9[0m
- [0m[DEBUG] CPU: family 06, model 9e, stepping 09[0m
- [0m[DEBUG] CPU: vendor Intel device 906e9[0m
- [0m[DEBUG] CPU: family 06, model 9e, stepping 09[0m
- [0m[DEBUG] Clearing out pending MCEs[0m
- [0m[DEBUG] Clearing out pending MCEs[0m
- [0m[DEBUG] cpu: energy policy set to 6[0m
- [0m[DEBUG] cpu: energy policy set to 6[0m
- [0m[DEBUG] Skip microcode update[0m
- [0m[INFO ] CPU #6 initialized[0m
- [0m[DEBUG] Skip microcode update[0m
- [0m[INFO ] CPU #7 initialized[0m
- [0m[DEBUG] Clearing out pending MCEs[0m
- [0m[DEBUG] CPU: vendor Intel device 906e9[0m
- [0m[DEBUG] CPU: family 06, model 9e, stepping 09[0m
- [0m[DEBUG] CPU: vendor Intel device 906e9[0m
- [0m[DEBUG] CPU: family 06, model 9e, stepping 09[0m
- [0m[DEBUG] Clearing out pending MCEs[0m
- [0m[DEBUG] Clearing out pending MCEs[0m
- [0m[DEBUG] cpu: energy policy set to 6[0m
- [0m[DEBUG] cpu: energy policy set to 6[0m
- [0m[DEBUG] Skip microcode update[0m
- [0m[INFO ] CPU #4 initialized[0m
- [0m[DEBUG] Skip microcode update[0m
- [0m[INFO ] CPU #5 initialized[0m
- [0m[DEBUG] cpu: energy policy set to 6[0m
- [0m[DEBUG] Skip microcode update[0m
- [0m[INFO ] CPU #1 initialized[0m
- [0m[INFO ] bsp_do_flight_plan done after 691 msecs.[0m
- [0m[DEBUG] CPU: frequency set to 4200 MHz[0m
- [0m[DEBUG] Enabling SMIs.[0m
- [0m[DEBUG] Locking SMM.[0m
- [0m[DEBUG] VMX status: enabled[0m
- [0m[DEBUG] VMX status: enabled[0m
- [0m[DEBUG] IA32_FEATURE_CONTROL status: locked[0m
- [0m[DEBUG] VMX status: enabled[0m
- [0m[DEBUG] VMX status: enabled[0m
- [0m[DEBUG] IA32_FEATURE_CONTROL status: locked[0m
- [0m[DEBUG] IA32_FEATURE_CONTROL status: locked[0m
- [0m[DEBUG] VMX status: enabled[0m
- [0m[DEBUG] VMX status: enabled[0m
- [0m[DEBUG] IA32_FEATURE_CONTROL status: locked[0m
- [0m[DEBUG] IA32_FEATURE_CONTROL status: locked[0m
- [0m[DEBUG] VMX status: enabled[0m
- [0m[DEBUG] VMX status: enabled[0m
- [0m[DEBUG] IA32_FEATURE_CONTROL status: locked[0m
- [0m[DEBUG] IA32_FEATURE_CONTROL status: locked[0m
- [0m[DEBUG] BS: BS_DEV_INIT_CHIPS entry times (exec / console): 532 / 465 ms[0m
- [0m[DEBUG] IA32_FEATURE_CONTROL status: locked[0m
- [0m[INFO ] POST: 0x71[0m
- [0m[DEBUG] WEAK: src/soc/intel/skylake/chip.c/mainboard_silicon_init_params called[0m
- [0m[INFO ] POST: 0x93[0m
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