module module_name (<ports declaration>);

// stage 0
<stage 0 output buffers declaration>
always @(posedge clk_i)
    begin
    if (rst_i) begin st0_reg0 <= 0; … end;    // clearing request at stage 0
    else begin st0_reg0 <= in0 + in1; … end;  // stage 0 processing of inputs
    end

// stage 1
<stage 1 output buffers declaration>
always @(posedge clk_i)
    begin
    if (rst_i) begin st1_reg0 <= 0; … end;    // clearing request at stage 1
    else begin st1_reg0 <= st0_reg0 + st0_reg1 ; … end; // stage 1 processing
    end

…

endmodule