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Man Page - rbx_analyze_rc011

Jun 9th, 2015
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  1. Rubix STA-Setup PrimeTime Custom Command, ARM Ltd.
  2.  
  3. NAME
  4. rbx_analyze_rc011
  5.  
  6. SYNTAX
  7. rbx_analyze_rc011 -pt_log <primetime_log_file_with_rc011> [-check_type setup | hold] [-rc011_slack_lesser_than lesser_slack_limit]
  8.  
  9. ARGUMENTS
  10. -pt_log <primetime_log_file_with_rc011>
  11. This is the log file which contains the RC-011 error messages.
  12. The log files cannot be in compressed format (zip, gzip etc).
  13. This is a mandatory option.
  14.  
  15. -check_type [setup | hold]
  16. Default: setup
  17. o setup - Checks the impact of RC-011 messages on setup timing.
  18. o hold - Checks the impact of RC-011 messages on hold timing.
  19.  
  20. -rc011_slack_lesser_than <lesser_slack_limit>
  21. Default: 0
  22. This command calculates the setup or hold slacks that would result
  23. on certain paths after the RC-011 errors related to those paths are
  24. fixed. This option directs the command to report only the paths with
  25. slack less (more negative) than lesser_slack_limit.
  26.  
  27. DESCRIPTION
  28. RC-011 errors of one or more timing arcs in a path may not cause timing violation
  29. if the slack of that path is considerably higher than the sum of those arc delays.
  30. This command reads the RC-011 errors from a log file and checks the impact of each
  31. error on paths slack. If there are multiple cells in a path with RC-011 error then
  32. the cumulative effect of in-accuracies in delay calculation of all these cells is taken
  33. into account. Designers can use the report generted by this command to make a decision
  34. of wheather they want to fix the errors or waive them.
  35. Generally setup and hold analysis are run as different scenarios and consequently different
  36. log files could be generated. -check_type option of this command could be used to
  37. analyze the impact on either setup or hold timing based on the RC-011 errors present
  38. in the log file specified with -pt_log option. This command analyzes both scenarios where
  39. the RC-011 is caused by output load being outside the table limits and input slew being
  40. outside the table limits.
  41.  
  42. EXAMPLE
  43. In the following example a STA session with RC-011 errors is restored. Then in this restored
  44. session the following command is run to check the impact of RC-011 errors on the hold timing.
  45. The log file "design_hold_scenario.log" is generated by the run that created "scen1_hold_anal.session".
  46.  
  47. pt_shell> restore_session scen1_hold_anal.session
  48. pt_shell> rbx_analyze_rc011 -pt_log design_hold_scenario.log -check_type hold -rc011_slack_lesser_than 0.400
  49.  
  50.  
  51. *********************************************************************************************
  52. Rubix Custom Report
  53.  
  54. Report : rbx_analyze_rc011
  55. -pt_log design_hold_scenario.log
  56. -check_type hold
  57. -rc011_slack_lesser_than 0.400
  58. Design : my_design
  59. Version : J-2014.06-SP3
  60. Date : Fri Apr 3 14:33:43 2015
  61. *********************************************************************************************
  62. Type:
  63. OL - Over Table Limit
  64. UL - Under Table Limit
  65.  
  66.  
  67. Type RC011-Slack Path-hold-Slack Endpoint
  68. ---- ----------- ---------------- --------
  69. Stage Delay RC011-Data-Pins
  70. ----------- ---------------
  71.  
  72. OL 0.381 0.380 u_columbus64_apollo_core_integration/u_columbus64_apollo_core/u_CORTEXA53/u_ca53_l2/u_ca53_l2noram/u_ca53governor/g_governor_cpu_3_u_governor_cpu/u_governor_cpu_slice/cp_gov_wdata_rs_o_reg_0/R
  73. 0.029 u_columbus64_apollo_core_integration/u_columbus64_apollo_core/u_CORTEXA53/u_ca53_l2/u_ca53_l2noram/u_ca53governor/g_governor_cpu_3_u_governor_cpu/u_governor_cpu_slice/PlaceOpt_FE_OFC34940_n_1599/A
  74.  
  75. OL 0.385 0.384 u_columbus64_apollo_core_integration/u_columbus64_apollo_core/u_CORTEXA53/u_ca53_l2/u_ca53_l2noram/u_ca53governor/g_governor_cpu_3_u_governor_cpu/u_governor_cpu_slice/excl_mon_cleared_o_reg/R
  76. 0.029 u_columbus64_apollo_core_integration/u_columbus64_apollo_core/u_CORTEXA53/u_ca53_l2/u_ca53_l2noram/u_ca53governor/g_governor_cpu_3_u_governor_cpu/u_governor_cpu_slice/PlaceOpt_FE_OFC34940_n_1599/A
  77.  
  78. OL 0.341 0.340 u_columbus64_apollo_core_integration/u_columbus64_apollo_core/u_CORTEXA53/u_ca53_l2/u_ca53_l2noram/u_ca53governor/g_governor_cpu_3_u_governor_cpu/u_governor_cpu_slice/gov_cp_ack_reg/R
  79. 0.029 u_columbus64_apollo_core_integration/u_columbus64_apollo_core/u_CORTEXA53/u_ca53_l2/u_ca53_l2noram/u_ca53governor/g_governor_cpu_3_u_governor_cpu/u_governor_cpu_slice/PlaceOpt_FE_OFC34940_n_1599/A
  80.  
  81. OL 0.366 0.365 u_columbus64_apollo_core_integration/u_columbus64_apollo_core/u_CORTEXA53/u_ca53_l2/u_ca53_l2noram/u_ca53governor/g_governor_cpu_3_u_governor_cpu/u_governor_cpu_slice/gov_int_active_reg/R
  82. 0.029 u_columbus64_apollo_core_integration/u_columbus64_apollo_core/u_CORTEXA53/u_ca53_l2/u_ca53_l2noram/u_ca53governor/g_governor_cpu_3_u_governor_cpu/u_governor_cpu_slice/PlaceOpt_FE_OFC34940_n_1599/A
  83.  
  84. OL 0.390 0.389 u_columbus64_apollo_core_integration/u_columbus64_apollo_core/u_CORTEXA53/u_ca53_l2/u_ca53_l2noram/u_ca53governor/g_governor_cpu_3_u_governor_cpu/u_governor_cpu_slice/gov_mbistreq_cpu_o_reg/R
  85. 0.029 u_columbus64_apollo_core_integration/u_columbus64_apollo_core/u_CORTEXA53/u_ca53_l2/u_ca53_l2noram/u_ca53governor/g_governor_cpu_3_u_governor_cpu/u_governor_cpu_slice/PlaceOpt_FE_OFC34940_n_1599/A
  86.  
  87. OL 0.364 0.363 u_columbus64_apollo_core_integration/u_columbus64_apollo_core/u_CORTEXA53/u_ca53_l2/u_ca53_l2noram/u_ca53governor/g_governor_cpu_3_u_governor_cpu/u_governor_cpu_slice/vsei_level_req_reg/R
  88. 0.029 u_columbus64_apollo_core_integration/u_columbus64_apollo_core/u_CORTEXA53/u_ca53_l2/u_ca53_l2noram/u_ca53governor/g_governor_cpu_3_u_governor_cpu/u_governor_cpu_slice/PlaceOpt_FE_OFC34940_n_1599/A
  89.  
  90. UL 0.070 0.100 u_columbus64_apollo_core_integration/u_columbus64_apollo_core/u_CORTEXA53/u_ca53_l2/u_ca53_l2noram/u_ca53scu/u_scu_master/g_ace_u_master_ace/scu_ext_dw_data_reg_56/SI
  91. 0.037 u_columbus64_apollo_core_integration/u_columbus64_apollo_core/u_CORTEXA53/u_ca53_l2/u_ca53_l2noram/u_ca53scu/u_scu_master/g_ace_u_master_ace/DFT_multi_mode_115/B0
  92.  
  93.  
  94.  
  95. Type RC011-Clock-Pin
  96. ---- ---------------
  97. OL, UL u_columbus64_apollo_core_integration/u_columbus64_apollo_core/u_CORTEXA53/u_ca53_l2/u_ca53_l2noram/u_ca53governor/g_governor_cpu_3_u_governor_cpu/u_governor_cpu_slice/AZ_cdb_INV_cpuclk_post_occ_G1_L66_795/A
  98. OL u_columbus64_apollo_core_integration/u_columbus64_apollo_core/u_CORTEXA53/u_ca53_l2/u_ca53_l2noram/u_ca53governor/g_governor_cpu_3_u_governor_cpu/u_governor_cpu_slice/inv_scu_tag_state_reg/CK
  99.  
  100. 1
  101.  
  102.  
  103. Note that the "Type" column shows if the extrapolation is done over the table limit
  104. or below the table limit. The first part of the report shows the data pins with RC-011
  105. violations and the second part shows the clock pins with this vioaltion. The command
  106. does not do any triaging on the clock pins since in general such violations on clock
  107. circuitry cannot be waived and have to be fixed.
  108.  
  109.  
  110. Rubix STA-Setup PrimeTime Custom Command, ARM Ltd.
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