/************************************************************************
Avalon-MM Interface for Convolution IP Core

Register Map:

 0-3 : 4x 32bit AES Key
 4-7 : 4x 32bit AES Encrypted Message
 8-11: 4x 32bit AES Decrypted Message
   12: Not Used
    13: Not Used
   14: 32bit Start Register
   15: 32bit Done Register

************************************************************************/

module avalon_conv_interface (
    // Avalon Clock Input
    input logic CLK,

    // Avalon Reset Input
    input logic RESET,

    // Avalon-MM Slave Signals
    input  logic AVL_READ,                  // Avalon-MM Read
    input  logic AVL_WRITE,                 // Avalon-MM Write
    input  logic AVL_CS,                        // Avalon-MM Chip Select
    input  logic [3:0] AVL_BYTE_EN,     // Avalon-MM Byte Enable
    input  logic [6:0] AVL_ADDR,            // Avalon-MM Address
    input  logic [31:0] AVL_WRITEDATA,  // Avalon-MM Write Data
    output logic [31:0] AVL_READDATA,   // Avalon-MM Read Data

    // Exported Conduit
    output logic [31:0] EXPORT_DATA     // Exported Conduit Signal to LEDs
);

// inputs to mat_mul_accl module
logic MM_START;
logic MM_DONE;
logic SUM;
// what goes to conv2d
logic [31:0] mat1 [74:0];
logic [31:0] mat2 [26:0];
logic [31:0] outmat [8:0];


logic [31:0] reggy [112:0];
logic [31:0] startReg;
logic [31:0] doneReg;

assign MMStart = startReg[0];

mat1[0] = reggy[0];
mat1[1] = reggy[1];
mat1[2] = reggy[2];
mat1[3] = reggy[3];
mat1[4] = reggy[4];
mat1[5] = reggy[5];
mat1[6] = reggy[6];
mat1[7] = reggy[7];
mat1[8] = reggy[8];
mat1[9] = reggy[9];
mat1[10] = reggy[10];
mat1[11] = reggy[11];
mat1[12] = reggy[12];
mat1[13] = reggy[13];
mat1[14] = reggy[14];
mat1[15] = reggy[15];
mat1[16] = reggy[16];
mat1[17] = reggy[17];
mat1[18] = reggy[18];
mat1[19] = reggy[19];
mat1[20] = reggy[20];
mat1[21] = reggy[21];
mat1[22] = reggy[22];
mat1[23] = reggy[23];
mat1[24] = reggy[24];

mat1[25] = reggy[25];
mat1[26] = reggy[26];
mat1[27] = reggy[27];
mat1[28] = reggy[28];
mat1[29] = reggy[29];
mat1[30] = reggy[30];
mat1[31] = reggy[31];
mat1[32] = reggy[32];
mat1[33] = reggy[33];
mat1[34] = reggy[34];
mat1[35] = reggy[35];
mat1[36] = reggy[36];
mat1[37] = reggy[37];
mat1[38] = reggy[38];
mat1[39] = reggy[39];
mat1[40] = reggy[40];
mat1[41] = reggy[41];
mat1[42] = reggy[42];
mat1[43] = reggy[43];
mat1[44] = reggy[44];
mat1[45] = reggy[45];
mat1[46] = reggy[46];
mat1[47] = reggy[47];
mat1[48] = reggy[48];
mat1[49] = reggy[49];

mat1[50] = reggy[50];
mat1[51] = reggy[51];
mat1[52] = reggy[52];
mat1[53] = reggy[53];
mat1[54] = reggy[54];
mat1[55] = reggy[55];
mat1[56] = reggy[56];
mat1[57] = reggy[57];
mat1[58] = reggy[58];
mat1[59] = reggy[59];
mat1[60] = reggy[60];
mat1[61] = reggy[61];
mat1[62] = reggy[62];
mat1[63] = reggy[63];
mat1[64] = reggy[64];
mat1[65] = reggy[65];
mat1[66] = reggy[66];
mat1[67] = reggy[67];
mat1[68] = reggy[68];
mat1[69] = reggy[69];
mat1[70] = reggy[70];
mat1[71] = reggy[71];
mat1[72] = reggy[72];
mat1[73] = reggy[73];
mat1[74] = reggy[74];

mat2[0] = reggy[75];
mat2[1] = reggy[76];
mat2[2] = reggy[77];
mat2[3] = reggy[78];
mat2[4] = reggy[79];
mat2[5] = reggy[80];
mat2[6] = reggy[81];
mat2[7] = reggy[82];
mat2[8] = reggy[83];
mat2[9] = reggy[84];
mat2[10] = reggy[85];
mat2[11] = reggy[86];
mat2[12] = reggy[87];
mat2[13] = reggy[88];
mat2[14] = reggy[89];
mat2[15] = reggy[90];
mat2[16] = reggy[91];
mat2[17] = reggy[92];
mat2[18] = reggy[93];
mat2[19] = reggy[94];
mat2[20] = reggy[95];
mat2[21] = reggy[96];
mat2[22] = reggy[97];
mat2[23] = reggy[98];
mat2[24] = reggy[99];
mat2[25] = reggy[100];
mat2[26] = reggy[101];

// reggy[0:8] - input1 and reggy[9:17] - input2
// reggy[18:26] - output?
//mat_mul_accl matmult(.*);

assign doneReg[0] = MM_DONE;
always_ff @ (posedge CLK)
begin
    // Reset is active HIGH
    if(RESET)
    begin
        for(int i = 0; i < 32; i++)
        begin
            reggy[i] <= 32'b0;
        end
    end
    else if(AVL_CS)
    begin
        if(AVL_WRITE)
        begin
            // depending on which register is the destination register, load contents from data bus into that register
            case(AVL_ADDR)
                4'd27 : startReg[0] <= AVL_WRITEDATA;
                default: reggy[AVL_ADDR] <= AVL_WRITEDATA;
            endcase

        end

    end
end

    // depending on SR1 register, output corresponding register contents to SR1_OUT


    // Should this be in an always_comb block?
    // How do you account for 0 cycle wait latency?
    assign EXPORT_DATA = {reggy[4][31:16], reggy[7][15:0]};

always_comb
begin
    if(AVL_CS & AVL_READ)
    begin
        // depending on which register is the destination register, load contents from data bus into
        // that register
        case(AVL_ADDR)
            4'd28 : AVL_READDATA = doneReg[0];
            default: AVL_READDATA = reggy[AVL_ADDR];
        endcase
    end
    else
    begin
        AVL_READDATA = 32'bx;
    end
end

endmodule