module mux_builtin (
    input [1:0] sel_bi
    , input [3:0] data_bi
    , output q_o
);

logic [1:0] sel_not;
not (sel_not[0], sel_bi[0]);
not (sel_not[1], sel_bi[1]);

logic sel00, sel01, sel10, sel11;
and (sel00, sel_not[0], sel_not[1]);
and (sel01, sel_bi [0], sel_not[1]);
and (sel10, sel_not[0], sel_bi [1]);
and (sel11, sel_bi [0], sel_bi [1]);

logic [3:0] data_gated;
and (data_gated[0], data_bi[0], sel00);
and (data_gated[1], data_bi[1], sel01);
and (data_gated[2], data_bi[2], sel10);
and (data_gated[3], data_bi[3], sel11);

logic or_inter0, or_inter1;
or (or_inter0, data_gated[0], data_gated[1]);
or (or_inter1, data_gated[2], data_gated[3]);
or (q_o,       or_inter0,     or_inter1);

endmodule