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- Args: ./llc -debug -debug-node-output=id -debug-node-op-inline=Cru ../../../llvm/test/CodeGen/ARM/crash-shufflevector.ll
- Subtarget features: SSELevel 7, 3DNowLevel 0, 64bit 1
- Computing probabilities for
- === f
- Initial selection DAG: BB#0 'f:'
- SelectionDAG has 23 nodes:
- Node0: ch = EntryToken [ORD=1]
- Node1: v4i8 = undef [ORD=1]
- Node2: v16i8 = undef
- Node3: i32 = GlobalAddress<void (<16 x i8>)* @g> 0
- Node4: i32 = TargetConstant<0> [ORD=4]
- Node5: v16i8 = Register %XMM0 [ORD=4]
- Node0: <multiple use>
- i32 0: <multiple use>
- Node6: ch,glue = callseq_start Node0, i32 0 [ORD=4]
- Node5<reg %XMM0 [ORD=4]>: <multiple use>
- Node0: <multiple use>
- Node7: v4i32 = Register %vreg0 [ORD=1]
- Node8: v4i32,ch = CopyFromReg Node0, Node7<reg %vreg0 [ORD=1]> [ORD=1]
- Node9: v4i8 = truncate Node8 [ORD=1]
- Node1<v4i8 undef>: <multiple use>
- Node1<v4i8 undef>: <multiple use>
- Node1<v4i8 undef>: <multiple use>
- Node10: v16i8 = concat_vectors Node9, Node1<v4i8 undef>, Node1<v4i8 undef>, Node1<v4i8 undef> [ORD=1]
- Node0: <multiple use>
- Node11: v4i32 = Register %vreg1 [ORD=2]
- Node12: v4i32,ch = CopyFromReg Node0, Node11<reg %vreg1 [ORD=2]> [ORD=2]
- Node13: v4i8 = truncate Node12 [ORD=2]
- Node1<v4i8 undef>: <multiple use>
- Node1<v4i8 undef>: <multiple use>
- Node1<v4i8 undef>: <multiple use>
- Node14: v16i8 = concat_vectors Node13, Node1<v4i8 undef>, Node1<v4i8 undef>, Node1<v4i8 undef> [ORD=2]
- Node15: v16i8 = vector_shuffle Node10, Node14<0,1,2,3,4,5,6,7,8,9,10,11,16,17,18,19> [ORD=3]
- Node16: ch,glue = CopyToReg Node6, Node5<reg %XMM0 [ORD=4]>, Node15 [ORD=4]
- Node16: <multiple use>
- Node17: i32 = TargetGlobalAddress<void (<16 x i8>)* @g> 0 [ORD=4]
- Node5<reg %XMM0 [ORD=4]>: <multiple use>
- Node18: Untyped = RegisterMask [ORD=4]
- Node16: <multiple use>
- Node19: ch,glue = X86ISD::CALL Node16, Node17, Node5<reg %XMM0 [ORD=4]>, Node18, Node16:1 [ORD=4]
- Node19: <multiple use>
- i32 0: <multiple use>
- i32 0: <multiple use>
- Node19: <multiple use>
- Node20: ch,glue = callseq_end Node19, i32 0, i32 0, Node19:1 [ORD=4]
- Node21: i16 = TargetConstant<0>
- Node22: ch = X86ISD::RET_FLAG Node20, i16 0
- Optimized lowered selection DAG: BB#0 'f:'
- SelectionDAG has 21 nodes:
- Node0: ch = EntryToken [ORD=1]
- Node1: v4i8 = undef [ORD=1]
- Node4: i32 = TargetConstant<0> [ORD=4]
- Node5: v16i8 = Register %XMM0 [ORD=4]
- Node0: <multiple use>
- i32 0: <multiple use>
- Node6: ch,glue = callseq_start Node0, i32 0 [ORD=4]
- Node5<reg %XMM0 [ORD=4]>: <multiple use>
- Node0: <multiple use>
- Node7: v4i32 = Register %vreg0 [ORD=1]
- Node8: v4i32,ch = CopyFromReg Node0, Node7<reg %vreg0 [ORD=1]> [ORD=1]
- Node9: v4i8 = truncate Node8 [ORD=1]
- Node1<v4i8 undef>: <multiple use>
- Node1<v4i8 undef>: <multiple use>
- Node1<v4i8 undef>: <multiple use>
- Node10: v16i8 = concat_vectors Node9, Node1<v4i8 undef>, Node1<v4i8 undef>, Node1<v4i8 undef> [ORD=1]
- Node0: <multiple use>
- Node11: v4i32 = Register %vreg1 [ORD=2]
- Node12: v4i32,ch = CopyFromReg Node0, Node11<reg %vreg1 [ORD=2]> [ORD=2]
- Node13: v4i8 = truncate Node12 [ORD=2]
- Node1<v4i8 undef>: <multiple use>
- Node1<v4i8 undef>: <multiple use>
- Node1<v4i8 undef>: <multiple use>
- Node14: v16i8 = concat_vectors Node13, Node1<v4i8 undef>, Node1<v4i8 undef>, Node1<v4i8 undef> [ORD=2]
- Node15: v16i8 = vector_shuffle Node10, Node14<0,1,2,3,4,5,6,7,8,9,10,11,16,17,18,19> [ORD=3]
- Node16: ch,glue = CopyToReg Node6, Node5<reg %XMM0 [ORD=4]>, Node15 [ORD=4]
- Node16: <multiple use>
- Node17: i32 = TargetGlobalAddress<void (<16 x i8>)* @g> 0 [ORD=4]
- Node5<reg %XMM0 [ORD=4]>: <multiple use>
- Node18: Untyped = RegisterMask [ORD=4]
- Node16: <multiple use>
- Node19: ch,glue = X86ISD::CALL Node16, Node17, Node5<reg %XMM0 [ORD=4]>, Node18, Node16:1 [ORD=4]
- Node19: <multiple use>
- i32 0: <multiple use>
- i32 0: <multiple use>
- Node19: <multiple use>
- Node20: ch,glue = callseq_end Node19, i32 0, i32 0, Node19:1 [ORD=4]
- Node21: i16 = TargetConstant<0>
- Node22: ch = X86ISD::RET_FLAG Node20, i16 0
- Legally typed node: Node21: i16 = TargetConstant<0> [ID=0]
- Legally typed node: Node18: Untyped = RegisterMask [ORD=4] [ID=0]
- Legally typed node: Node17: i32 = TargetGlobalAddress<void (<16 x i8>)* @g> 0 [ORD=4] [ID=0]
- Legally typed node: Node5: v16i8 = Register %XMM0 [ORD=4] [ID=0]
- Legally typed node: Node4: i32 = TargetConstant<0> [ORD=4] [ID=0]
- Promote integer result: Node1: v4i8 = undef [ORD=1] [ID=0]
- Legally typed node: Node2: v4i32 = undef [ID=0]
- Legally typed node: Node11: v4i32 = Register %vreg1 [ORD=2] [ID=0]
- Legally typed node: Node7: v4i32 = Register %vreg0 [ORD=1] [ID=0]
- Legally typed node: Node0: ch = EntryToken [ORD=1] [ID=0]
- Legally typed node: Node8: v4i32,ch = CopyFromReg Node0, Node7<reg %vreg0 [ORD=1] [ID=-3]> [ORD=1] [ID=0]
- Promote integer result: Node9: v4i8 = truncate Node8 [ORD=1] [ID=0]
- Promote integer operand: Node10: v16i8 = concat_vectors Node9, Node1<v4i8 undef>, Node1<v4i8 undef>, Node1<v4i8 undef> [ORD=1] [ID=0]
- Legally typed node: Node23: i8 = undef [ID=0]
- Legally typed node: Node24: i32 = Constant<3> [ID=0]
- Legally typed node: Node25: i32 = extract_vector_elt Node8, i32 3 [ID=0]
- Legally typed node: Node26: i8 = truncate Node25 [ID=0]
- Legally typed node: Node27: i32 = Constant<2> [ID=0]
- Legally typed node: Node28: i32 = extract_vector_elt Node8, i32 2 [ID=0]
- Legally typed node: Node29: i8 = truncate Node28 [ID=0]
- Legally typed node: Node30: i32 = Constant<1> [ID=0]
- Legally typed node: Node31: i32 = extract_vector_elt Node8, i32 1 [ID=0]
- Legally typed node: Node32: i8 = truncate Node31 [ID=0]
- Legally typed node: Node3: i32 = Constant<0> [ID=0]
- Legally typed node: Node33: i32 = extract_vector_elt Node8, i32 0 [ID=0]
- Legally typed node: Node34: i8 = truncate Node33 [ID=0]
- Legally typed node: Node35: v16i8 = BUILD_VECTOR Node34, Node32, Node29, Node26, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef> [ID=0]
- Legally typed node: Node12: v4i32,ch = CopyFromReg Node0, Node11<reg %vreg1 [ORD=2] [ID=-3]> [ORD=2] [ID=0]
- Promote integer result: Node13: v4i8 = truncate Node12 [ORD=2] [ID=0]
- Promote integer operand: Node14: v16i8 = concat_vectors Node13, Node1<v4i8 undef>, Node1<v4i8 undef>, Node1<v4i8 undef> [ORD=2] [ID=0]
- Legally typed node: Node36: i32 = extract_vector_elt Node12, i32 3 [ID=0]
- Legally typed node: Node37: i8 = truncate Node36 [ID=0]
- Legally typed node: Node38: i32 = extract_vector_elt Node12, i32 2 [ID=0]
- Legally typed node: Node39: i8 = truncate Node38 [ID=0]
- Legally typed node: Node40: i32 = extract_vector_elt Node12, i32 1 [ID=0]
- Legally typed node: Node41: i8 = truncate Node40 [ID=0]
- Legally typed node: Node42: i32 = extract_vector_elt Node12, i32 0 [ID=0]
- Legally typed node: Node43: i8 = truncate Node42 [ID=0]
- Legally typed node: Node44: v16i8 = BUILD_VECTOR Node43, Node41, Node39, Node37, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef> [ID=0]
- Legally typed node: Node15: v16i8 = vector_shuffle Node35, Node44<0,1,2,3,4,5,6,7,8,9,10,11,16,17,18,19> [ORD=3] [ID=0]
- Legally typed node: Node6: ch,glue = callseq_start Node0, i32 0 [ORD=4] [ID=0]
- Legally typed node: Node16: ch,glue = CopyToReg Node6, Node5<reg %XMM0 [ORD=4] [ID=-3]>, Node15 [ORD=4] [ID=0]
- Legally typed node: Node19: ch,glue = X86ISD::CALL Node16, Node17, Node5<reg %XMM0 [ORD=4] [ID=-3]>, Node18, Node16:1 [ORD=4] [ID=0]
- Legally typed node: Node20: ch,glue = callseq_end Node19, i32 0, i32 0, Node19:1 [ORD=4] [ID=0]
- Legally typed node: Node22: ch = X86ISD::RET_FLAG Node20, i16 0 [ID=0]
- Legally typed node: Node45: ch = handlenode Node22 [ID=0]
- Type-legalized selection DAG: BB#0 'f:'
- SelectionDAG has 39 nodes:
- Node0: ch = EntryToken [ORD=1] [ID=-3]
- Node0: <multiple use>
- Node7: v4i32 = Register %vreg0 [ORD=1] [ID=-3]
- Node8: v4i32,ch = CopyFromReg Node0, Node7<reg %vreg0 [ORD=1] [ID=-3]> [ORD=1] [ID=-3]
- Node0: <multiple use>
- Node11: v4i32 = Register %vreg1 [ORD=2] [ID=-3]
- Node12: v4i32,ch = CopyFromReg Node0, Node11<reg %vreg1 [ORD=2] [ID=-3]> [ORD=2] [ID=-3]
- Node4: i32 = TargetConstant<0> [ORD=4] [ID=-3]
- Node5: v16i8 = Register %XMM0 [ORD=4] [ID=-3]
- Node0: <multiple use>
- i32 0: <multiple use>
- Node6: ch,glue = callseq_start Node0, i32 0 [ORD=4] [ID=-3]
- Node5<reg %XMM0 [ORD=4] [ID=-3]>: <multiple use>
- Node8: <multiple use>
- i32 0: <multiple use>
- Node33: i32 = extract_vector_elt Node8, i32 0 [ID=-3]
- Node34: i8 = truncate Node33 [ID=-3]
- Node8: <multiple use>
- i32 1: <multiple use>
- Node31: i32 = extract_vector_elt Node8, i32 1 [ID=-3]
- Node32: i8 = truncate Node31 [ID=-3]
- Node8: <multiple use>
- i32 2: <multiple use>
- Node28: i32 = extract_vector_elt Node8, i32 2 [ID=-3]
- Node29: i8 = truncate Node28 [ID=-3]
- Node8: <multiple use>
- i32 3: <multiple use>
- Node25: i32 = extract_vector_elt Node8, i32 3 [ID=-3]
- Node26: i8 = truncate Node25 [ID=-3]
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node35: v16i8 = BUILD_VECTOR Node34, Node32, Node29, Node26, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef> [ID=-3]
- Node12: <multiple use>
- i32 0: <multiple use>
- Node42: i32 = extract_vector_elt Node12, i32 0 [ID=-3]
- Node43: i8 = truncate Node42 [ID=-3]
- Node12: <multiple use>
- i32 1: <multiple use>
- Node40: i32 = extract_vector_elt Node12, i32 1 [ID=-3]
- Node41: i8 = truncate Node40 [ID=-3]
- Node12: <multiple use>
- i32 2: <multiple use>
- Node38: i32 = extract_vector_elt Node12, i32 2 [ID=-3]
- Node39: i8 = truncate Node38 [ID=-3]
- Node12: <multiple use>
- i32 3: <multiple use>
- Node36: i32 = extract_vector_elt Node12, i32 3 [ID=-3]
- Node37: i8 = truncate Node36 [ID=-3]
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node23<i8 undef>: <multiple use>
- Node44: v16i8 = BUILD_VECTOR Node43, Node41, Node39, Node37, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef> [ID=-3]
- Node15: v16i8 = vector_shuffle Node35, Node44<0,1,2,3,4,5,6,7,8,9,10,11,16,17,18,19> [ORD=3] [ID=-3]
- Node16: ch,glue = CopyToReg Node6, Node5<reg %XMM0 [ORD=4] [ID=-3]>, Node15 [ORD=4] [ID=-3]
- Node16: <multiple use>
- Node17: i32 = TargetGlobalAddress<void (<16 x i8>)* @g> 0 [ORD=4] [ID=-3]
- Node5<reg %XMM0 [ORD=4] [ID=-3]>: <multiple use>
- Node18: Untyped = RegisterMask [ORD=4] [ID=-3]
- Node16: <multiple use>
- Node19: ch,glue = X86ISD::CALL Node16, Node17, Node5<reg %XMM0 [ORD=4] [ID=-3]>, Node18, Node16:1 [ORD=4] [ID=-3]
- Node3: i32 = Constant<0> [ID=-3]
- Node30: i32 = Constant<1> [ID=-3]
- Node27: i32 = Constant<2> [ID=-3]
- Node24: i32 = Constant<3> [ID=-3]
- Node23: i8 = undef [ID=-3]
- Node19: <multiple use>
- i32 0: <multiple use>
- i32 0: <multiple use>
- Node19: <multiple use>
- Node20: ch,glue = callseq_end Node19, i32 0, i32 0, Node19:1 [ORD=4] [ID=-3]
- Node21: i16 = TargetConstant<0> [ID=-3]
- Node22: ch = X86ISD::RET_FLAG Node20, i16 0 [ID=-3]
- Replacing.3 Node37: i8 = truncate Node36 [ID=-3]
- With: Node10: i8 = extract_vector_elt Node9, i32 12
- Replacing.3 Node39: i8 = truncate Node38 [ID=-3]
- With: Node37: i8 = extract_vector_elt Node9, i32 8
- Replacing.3 Node41: i8 = truncate Node40 [ID=-3]
- With: Node39: i8 = extract_vector_elt Node9, i32 4
- Replacing.3 Node43: i8 = truncate Node42 [ID=-3]
- With: Node40: i8 = extract_vector_elt Node9, i32 0
- Replacing.3 Node44: v16i8 = BUILD_VECTOR Node40, Node39, Node37, Node10, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef> [ID=-3]
- With: Node43: v16i8 = vector_shuffle Node9, Node42<v16i8 undef><0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u>
- Replacing.3 Node26: i8 = truncate Node25 [ID=-3]
- With: Node39: i8 = extract_vector_elt Node40, i32 12
- Replacing.3 Node29: i8 = truncate Node28 [ID=-3]
- With: Node25: i8 = extract_vector_elt Node40, i32 8
- Replacing.3 Node32: i8 = truncate Node31 [ID=-3]
- With: Node28: i8 = extract_vector_elt Node40, i32 4
- Replacing.3 Node34: i8 = truncate Node33 [ID=-3]
- With: Node30: i8 = extract_vector_elt Node40, i32 0
- Replacing.3 Node35: v16i8 = BUILD_VECTOR Node30, Node28, Node25, Node39, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef>, Node23<i8 undef> [ID=-3]
- With: Node33: v16i8 = vector_shuffle Node40, Node42<v16i8 undef><0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u>
- Optimized type-legalized selection DAG: BB#0 'f:'
- SelectionDAG has 21 nodes:
- Node0: ch = EntryToken [ORD=1] [ID=-3]
- Node4: i32 = TargetConstant<0> [ORD=4] [ID=-3]
- Node5: v16i8 = Register %XMM0 [ORD=4] [ID=-3]
- Node0: <multiple use>
- i32 0: <multiple use>
- Node6: ch,glue = callseq_start Node0, i32 0 [ORD=4] [ID=-3]
- Node5<reg %XMM0 [ORD=4] [ID=-3]>: <multiple use>
- Node0: <multiple use>
- Node7: v4i32 = Register %vreg0 [ORD=1] [ID=-3]
- Node8: v4i32,ch = CopyFromReg Node0, Node7<reg %vreg0 [ORD=1] [ID=-3]> [ORD=1] [ID=-3]
- Node40: v16i8 = bitcast Node8
- Node42<v16i8 undef>: <multiple use>
- Node33: v16i8 = vector_shuffle Node40, Node42<v16i8 undef><0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u>
- Node0: <multiple use>
- Node11: v4i32 = Register %vreg1 [ORD=2] [ID=-3]
- Node12: v4i32,ch = CopyFromReg Node0, Node11<reg %vreg1 [ORD=2] [ID=-3]> [ORD=2] [ID=-3]
- Node9: v16i8 = bitcast Node12
- Node42<v16i8 undef>: <multiple use>
- Node43: v16i8 = vector_shuffle Node9, Node42<v16i8 undef><0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u>
- Node15: v16i8 = vector_shuffle Node33, Node43<0,1,2,3,4,5,6,7,8,9,10,11,16,17,18,19> [ORD=3] [ID=-3]
- Node16: ch,glue = CopyToReg Node6, Node5<reg %XMM0 [ORD=4] [ID=-3]>, Node15 [ORD=4] [ID=-3]
- Node16: <multiple use>
- Node17: i32 = TargetGlobalAddress<void (<16 x i8>)* @g> 0 [ORD=4] [ID=-3]
- Node5<reg %XMM0 [ORD=4] [ID=-3]>: <multiple use>
- Node18: Untyped = RegisterMask [ORD=4] [ID=-3]
- Node16: <multiple use>
- Node19: ch,glue = X86ISD::CALL Node16, Node17, Node5<reg %XMM0 [ORD=4] [ID=-3]>, Node18, Node16:1 [ORD=4] [ID=-3]
- Node42: v16i8 = undef
- Node19: <multiple use>
- i32 0: <multiple use>
- i32 0: <multiple use>
- Node19: <multiple use>
- Node20: ch,glue = callseq_end Node19, i32 0, i32 0, Node19:1 [ORD=4] [ID=-3]
- Node21: i16 = TargetConstant<0> [ID=-3]
- Node22: ch = X86ISD::RET_FLAG Node20, i16 0 [ID=-3]
- Legalized selection DAG: BB#0 'f:'
- SelectionDAG has 30 nodes:
- Node0: ch = EntryToken [ORD=1] [ID=0]
- Node4: i32 = TargetConstant<0> [ORD=4] [ID=3]
- Node5: v16i8 = Register %XMM0 [ORD=4] [ID=4]
- Node0: <multiple use>
- i32 0: <multiple use>
- Node6: ch,glue = callseq_start Node0, i32 0 [ORD=4] [ID=11]
- Node5<reg %XMM0 [ORD=4] [ID=4]>: <multiple use>
- Node3: <multiple use>
- Node3: <multiple use>
- Node0: <multiple use>
- Node11: v4i32 = Register %vreg1 [ORD=2] [ID=2]
- Node12: v4i32,ch = CopyFromReg Node0, Node11<reg %vreg1 [ORD=2] [ID=2]> [ORD=2] [ID=10]
- Node9: v16i8 = bitcast Node12 [ID=13]
- Node39: <multiple use>
- Node34: v16i8 = X86ISD::PSHUFB Node9, Node39
- Node30: v4i32 = bitcast Node34
- Node25: v4i32 = X86ISD::MOVSS Node3, Node30
- Node27: i8 = Constant<36>
- Node38: v4i32 = X86ISD::SHUFP Node3, Node25, i8 36
- Node28: v16i8 = bitcast Node38
- Node16: ch,glue = CopyToReg Node6, Node5<reg %XMM0 [ORD=4] [ID=4]>, Node28 [ORD=4] [ID=17]
- Node16: <multiple use>
- Node17: i32 = TargetGlobalAddress<void (<16 x i8>)* @g> 0 [ORD=4] [ID=5]
- Node5<reg %XMM0 [ORD=4] [ID=4]>: <multiple use>
- Node18: Untyped = RegisterMask [ORD=4] [ID=6]
- Node16: <multiple use>
- Node19: ch,glue = X86ISD::CALL Node16, Node17, Node5<reg %XMM0 [ORD=4] [ID=4]>, Node18, Node16:1 [ORD=4] [ID=18]
- Node0: <multiple use>
- Node7: v4i32 = Register %vreg0 [ORD=1] [ID=1]
- Node8: v4i32,ch = CopyFromReg Node0, Node7<reg %vreg0 [ORD=1] [ID=1]> [ORD=1] [ID=9]
- Node40: v16i8 = bitcast Node8 [ID=12]
- Node39: <multiple use>
- Node43: v16i8 = X86ISD::PSHUFB Node40, Node39
- Node3: v4i32 = bitcast Node43
- Node0: <multiple use>
- Node31: i32 = TargetConstantPool<<16 x i8> <i8 0, i8 4, i8 8, i8 12, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>> 0
- Node23: i32 = X86ISD::Wrapper Node31
- Node33: i32 = undef
- Node24: v2i64,ch = load Node0, Node23, Node33<i32 undef><LD16[ConstantPool]>
- Node39: v16i8 = bitcast Node24
- Node19: <multiple use>
- i32 0: <multiple use>
- i32 0: <multiple use>
- Node19: <multiple use>
- Node20: ch,glue = callseq_end Node19, i32 0, i32 0, Node19:1 [ORD=4] [ID=19]
- Node21: i16 = TargetConstant<0> [ID=7]
- Node22: ch = X86ISD::RET_FLAG Node20, i16 0 [ID=20]
- Optimized legalized selection DAG: BB#0 'f:'
- SelectionDAG has 30 nodes:
- Node0: ch = EntryToken [ORD=1] [ID=0]
- Node4: i32 = TargetConstant<0> [ORD=4] [ID=3]
- Node5: v16i8 = Register %XMM0 [ORD=4] [ID=4]
- Node0: <multiple use>
- i32 0: <multiple use>
- Node6: ch,glue = callseq_start Node0, i32 0 [ORD=4] [ID=11]
- Node5<reg %XMM0 [ORD=4] [ID=4]>: <multiple use>
- Node3: <multiple use>
- Node3: <multiple use>
- Node0: <multiple use>
- Node11: v4i32 = Register %vreg1 [ORD=2] [ID=2]
- Node12: v4i32,ch = CopyFromReg Node0, Node11<reg %vreg1 [ORD=2] [ID=2]> [ORD=2] [ID=10]
- Node9: v16i8 = bitcast Node12 [ID=13]
- Node39: <multiple use>
- Node34: v16i8 = X86ISD::PSHUFB Node9, Node39
- Node30: v4i32 = bitcast Node34
- Node25: v4i32 = X86ISD::MOVSS Node3, Node30
- Node27: i8 = Constant<36>
- Node38: v4i32 = X86ISD::SHUFP Node3, Node25, i8 36
- Node28: v16i8 = bitcast Node38
- Node16: ch,glue = CopyToReg Node6, Node5<reg %XMM0 [ORD=4] [ID=4]>, Node28 [ORD=4] [ID=17]
- Node16: <multiple use>
- Node17: i32 = TargetGlobalAddress<void (<16 x i8>)* @g> 0 [ORD=4] [ID=5]
- Node5<reg %XMM0 [ORD=4] [ID=4]>: <multiple use>
- Node18: Untyped = RegisterMask [ORD=4] [ID=6]
- Node16: <multiple use>
- Node19: ch,glue = X86ISD::CALL Node16, Node17, Node5<reg %XMM0 [ORD=4] [ID=4]>, Node18, Node16:1 [ORD=4] [ID=18]
- Node0: <multiple use>
- Node7: v4i32 = Register %vreg0 [ORD=1] [ID=1]
- Node8: v4i32,ch = CopyFromReg Node0, Node7<reg %vreg0 [ORD=1] [ID=1]> [ORD=1] [ID=9]
- Node40: v16i8 = bitcast Node8 [ID=12]
- Node39: <multiple use>
- Node43: v16i8 = X86ISD::PSHUFB Node40, Node39
- Node3: v4i32 = bitcast Node43
- Node0: <multiple use>
- Node31: i32 = TargetConstantPool<<16 x i8> <i8 0, i8 4, i8 8, i8 12, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>> 0
- Node23: i32 = X86ISD::Wrapper Node31
- Node33: i32 = undef
- Node24: v2i64,ch = load Node0, Node23, Node33<i32 undef><LD16[ConstantPool]>
- Node39: v16i8 = bitcast Node24
- Node19: <multiple use>
- i32 0: <multiple use>
- i32 0: <multiple use>
- Node19: <multiple use>
- Node20: ch,glue = callseq_end Node19, i32 0, i32 0, Node19:1 [ORD=4] [ID=19]
- Node21: i16 = TargetConstant<0> [ID=7]
- Node22: ch = X86ISD::RET_FLAG Node20, i16 0 [ID=20]
- ===== Instruction selection begins: BB#0 ''
- Selecting: Node22: ch = X86ISD::RET_FLAG Node20, i16 0 [ID=29]
- ISEL: Starting pattern match on root node: Node22: ch = X86ISD::RET_FLAG Node20, i16 0 [ID=29]
- Morphed node: Node22: ch = RET Node20
- ISEL: Match complete!
- => Node22: ch = RET Node20
- Selecting: Node20: ch,glue = callseq_end Node19, i32 0, i32 0, Node19:1 [ORD=4] [ID=28]
- ISEL: Starting pattern match on root node: Node20: ch,glue = callseq_end Node19, i32 0, i32 0, Node19:1 [ORD=4] [ID=28]
- Initial Opcode index to 82627
- Morphed node: Node20: i32,ch,glue = ADJCALLSTACKUP32 i32 0, i32 0, Node19, Node19:1 [ORD=4]
- ISEL: Match complete!
- => Node20: i32,ch,glue = ADJCALLSTACKUP32 i32 0, i32 0, Node19, Node19:1 [ORD=4]
- Selecting: Node19: ch,glue = X86ISD::CALL Node16, Node17, Node5<reg %XMM0 [ORD=4] [ID=4]>, Node18, Node16:1 [ORD=4] [ID=27]
- ISEL: Starting pattern match on root node: Node19: ch,glue = X86ISD::CALL Node16, Node17, Node5<reg %XMM0 [ORD=4] [ID=4]>, Node18, Node16:1 [ORD=4] [ID=27]
- Initial Opcode index to 65628
- Match failed at index 65634
- Continuing at 65695
- OpcodeSwitch from 65701 to 65705
- TypeSwitch[i32] from 65705 to 65719
- Morphed node: Node19: ch,glue = CALLpcrel32 Node17, Node5<reg %XMM0 [ORD=4] [ID=4]>, Node18, Node16, Node16:1 [ORD=4]
- ISEL: Match complete!
- => Node19: ch,glue = CALLpcrel32 Node17, Node5<reg %XMM0 [ORD=4] [ID=4]>, Node18, Node16, Node16:1 [ORD=4]
- Selecting: Node16: ch,glue = CopyToReg Node6, Node5<reg %XMM0 [ORD=4] [ID=4]>, Node28 [ORD=4] [ID=26]
- => Node16: ch,glue = CopyToReg Node6, Node5<reg %XMM0 [ORD=4] [ID=4]>, Node28 [ORD=4]
- Selecting: Node28: v16i8 = bitcast Node38 [ID=25]
- ISEL: Starting pattern match on root node: Node28: v16i8 = bitcast Node38 [ID=25]
- Initial Opcode index to 80865
- Match failed at index 80869
- Continuing at 80895
- Skipped scope entry (due to false predicate) at index 80900, continuing at 80942
- Skipped scope entry (due to false predicate) at index 80943, continuing at 80971
- Skipped scope entry (due to false predicate) at index 80972, continuing at 81000
- Skipped scope entry (due to false predicate) at index 81001, continuing at 81029
- Match failed at index 80898
- Continuing at 81030
- Match failed at index 81033
- Continuing at 81137
- Match failed at index 81139
- Continuing at 81213
- Match failed at index 81216
- Continuing at 81334
- TypeSwitch[v16i8] from 81341 to 81358
- ISEL: Match complete!
- => Node28: v16i8 = bitcast Node38 [ID=25]
- Selecting: Node38: v4i32 = X86ISD::SHUFP Node3, Node25, i8 36 [ID=24]
- ISEL: Starting pattern match on root node: Node38: v4i32 = X86ISD::SHUFP Node3, Node25, i8 36 [ID=24]
- Initial Opcode index to 101465
- Match failed at index 101471
- Continuing at 101692
- TypeSwitch[v4i32] from 101703 to 101706
- Skipped scope entry (due to false predicate) at index 101708, continuing at 101722
- Morphed node: Node38: v4i32 = SHUFPSrri Node3, Node25, i8 36
- ISEL: Match complete!
- => Node38: v4i32 = SHUFPSrri Node3, Node25, i8 36
- Selecting: Node25: v4i32 = X86ISD::MOVSS Node3, Node30 [ID=23]
- ISEL: Starting pattern match on root node: Node25: v4i32 = X86ISD::MOVSS Node3, Node30 [ID=23]
- Initial Opcode index to 115181
- TypeSwitch[v4i32] from 115185 to 115188
- Skipped scope entry (due to false predicate) at index 115190, continuing at 115213
- Created node: Node21: f32 = COPY_TO_REGCLASS Node30, i32 9
- Morphed node: Node25: v4i32 = MOVSSrr Node3, Node21
- ISEL: Match complete!
- => Node25: v4i32 = MOVSSrr Node3, Node21
- Selecting: Node30: v4i32 = bitcast Node34 [ID=22]
- ISEL: Starting pattern match on root node: Node30: v4i32 = bitcast Node34 [ID=22]
- Initial Opcode index to 80865
- Match failed at index 80869
- Continuing at 80895
- Skipped scope entry (due to false predicate) at index 80900, continuing at 80942
- Skipped scope entry (due to false predicate) at index 80943, continuing at 80971
- Skipped scope entry (due to false predicate) at index 80972, continuing at 81000
- Skipped scope entry (due to false predicate) at index 81001, continuing at 81029
- Match failed at index 80898
- Continuing at 81030
- Match failed at index 81033
- Continuing at 81137
- Match failed at index 81139
- Continuing at 81213
- Match failed at index 81216
- Continuing at 81334
- Skipped scope entry (due to false predicate) at index 81339, continuing at 81378
- Skipped scope entry (due to false predicate) at index 81379, continuing at 81418
- TypeSwitch[v4i32] from 81421 to 81431
- ISEL: Match complete!
- => Node30: v4i32 = bitcast Node34 [ID=22]
- Selecting: Node3: v4i32 = bitcast Node43 [ID=21]
- ISEL: Starting pattern match on root node: Node3: v4i32 = bitcast Node43 [ID=21]
- Initial Opcode index to 80865
- Match failed at index 80869
- Continuing at 80895
- Skipped scope entry (due to false predicate) at index 80900, continuing at 80942
- Skipped scope entry (due to false predicate) at index 80943, continuing at 80971
- Skipped scope entry (due to false predicate) at index 80972, continuing at 81000
- Skipped scope entry (due to false predicate) at index 81001, continuing at 81029
- Match failed at index 80898
- Continuing at 81030
- Match failed at index 81033
- Continuing at 81137
- Match failed at index 81139
- Continuing at 81213
- Match failed at index 81216
- Continuing at 81334
- Skipped scope entry (due to false predicate) at index 81339, continuing at 81378
- Skipped scope entry (due to false predicate) at index 81379, continuing at 81418
- TypeSwitch[v4i32] from 81421 to 81431
- ISEL: Match complete!
- => Node3: v4i32 = bitcast Node43 [ID=21]
- Selecting: Node34: v16i8 = X86ISD::PSHUFB Node9, Node39 [ID=20]
- ISEL: Starting pattern match on root node: Node34: v16i8 = X86ISD::PSHUFB Node9, Node39 [ID=20]
- Initial Opcode index to 110519
- Match failed at index 110534
- Continuing at 110617
- TypeSwitch[v16i8] from 110619 to 110622
- Skipped scope entry (due to false predicate) at index 110624, continuing at 110635
- Morphed node: Node34: v16i8 = PSHUFBrr Node9, Node39
- ISEL: Match complete!
- => Node34: v16i8 = PSHUFBrr Node9, Node39
- Selecting: Node43: v16i8 = X86ISD::PSHUFB Node40, Node39 [ID=19]
- ISEL: Starting pattern match on root node: Node43: v16i8 = X86ISD::PSHUFB Node40, Node39 [ID=19]
- Initial Opcode index to 110519
- Match failed at index 110534
- Continuing at 110617
- TypeSwitch[v16i8] from 110619 to 110622
- Skipped scope entry (due to false predicate) at index 110624, continuing at 110635
- Morphed node: Node43: v16i8 = PSHUFBrr Node40, Node39
- ISEL: Match complete!
- => Node43: v16i8 = PSHUFBrr Node40, Node39
- Selecting: Node39: v16i8 = bitcast Node24 [ID=18]
- ISEL: Starting pattern match on root node: Node39: v16i8 = bitcast Node24 [ID=18]
- Initial Opcode index to 80865
- Match failed at index 80869
- Continuing at 80895
- Skipped scope entry (due to false predicate) at index 80900, continuing at 80942
- Skipped scope entry (due to false predicate) at index 80943, continuing at 80971
- Skipped scope entry (due to false predicate) at index 80972, continuing at 81000
- Skipped scope entry (due to false predicate) at index 81001, continuing at 81029
- Match failed at index 80898
- Continuing at 81030
- Match failed at index 81041
- Continuing at 81137
- Match failed at index 81139
- Continuing at 81213
- Match failed at index 81216
- Continuing at 81334
- Skipped scope entry (due to false predicate) at index 81339, continuing at 81378
- Skipped scope entry (due to false predicate) at index 81379, continuing at 81418
- Skipped scope entry (due to false predicate) at index 81419, continuing at 81458
- Skipped scope entry (due to false predicate) at index 81459, continuing at 81498
- Skipped scope entry (due to false predicate) at index 81499, continuing at 81538
- TypeSwitch[v16i8] from 81541 to 81558
- ISEL: Match complete!
- => Node39: v16i8 = bitcast Node24 [ID=18]
- Selecting: Node24: v2i64,ch = load Node0, Node23, Node33<i32 undef><LD16[ConstantPool]> [ID=17]
- ISEL: Starting pattern match on root node: Node24: v2i64,ch = load Node0, Node23, Node33<i32 undef><LD16[ConstantPool]> [ID=17]
- Initial Opcode index to 75053
- Match failed at index 75065
- Continuing at 75083
- Match failed at index 75086
- Continuing at 75104
- Match failed at index 75107
- Continuing at 75125
- Match failed at index 75128
- Continuing at 75146
- Match failed at index 75147
- Continuing at 75191
- Match failed at index 75192
- Continuing at 75236
- Match failed at index 75237
- Continuing at 75300
- Match failed at index 75301
- Continuing at 75364
- Match failed at index 75367
- Continuing at 75387
- Match failed at index 75388
- Continuing at 75466
- Match failed at index 75468
- Continuing at 75693
- Match failed at index 75694
- Continuing at 75728
- Match failed at index 75729
- Continuing at 75763
- Continuing at 75764
- Match failed at index 75773
- Continuing at 75795
- Match failed at index 75804
- Continuing at 75908
- Match failed at index 75909
- Continuing at 75980
- Match failed at index 75984
- Continuing at 76115
- Match failed at index 76116
- Continuing at 76235
- TypeSwitch[v2i64] from 76239 to 76242
- Match failed at index 76246
- Continuing at 76264
- Skipped scope entry (due to false predicate) at index 76267, continuing at 76285
- MatchAddress: X86ISelAddressMode 0xbfc20690
- Base_Reg nul Base.FrameIndex 0
- Scale1
- IndexReg nul Disp 0
- GV nul CP nul
- ES nul JT-1 Align0
- Morphed node: Node24: v2i64,ch = MOVAPSrm Node39<reg %noreg>, i8 1, Node39<reg %noreg>, Node31, Node39<reg %noreg>, Node0<Mem:LD16[ConstantPool]>
- ISEL: Match complete!
- => Node24: v2i64,ch = MOVAPSrm Node39<reg %noreg>, i8 1, Node39<reg %noreg>, Node31, Node39<reg %noreg>, Node0<Mem:LD16[ConstantPool]>
- Selecting: Node9: v16i8 = bitcast Node12 [ID=16]
- ISEL: Starting pattern match on root node: Node9: v16i8 = bitcast Node12 [ID=16]
- Initial Opcode index to 80865
- Match failed at index 80869
- Continuing at 80895
- Skipped scope entry (due to false predicate) at index 80900, continuing at 80942
- Skipped scope entry (due to false predicate) at index 80943, continuing at 80971
- Skipped scope entry (due to false predicate) at index 80972, continuing at 81000
- Skipped scope entry (due to false predicate) at index 81001, continuing at 81029
- Match failed at index 80898
- Continuing at 81030
- Match failed at index 81033
- Continuing at 81137
- Match failed at index 81139
- Continuing at 81213
- Match failed at index 81216
- Continuing at 81334
- TypeSwitch[v16i8] from 81341 to 81358
- ISEL: Match complete!
- => Node9: v16i8 = bitcast Node12 [ID=16]
- Selecting: Node40: v16i8 = bitcast Node8 [ID=15]
- ISEL: Starting pattern match on root node: Node40: v16i8 = bitcast Node8 [ID=15]
- Initial Opcode index to 80865
- Match failed at index 80869
- Continuing at 80895
- Skipped scope entry (due to false predicate) at index 80900, continuing at 80942
- Skipped scope entry (due to false predicate) at index 80943, continuing at 80971
- Skipped scope entry (due to false predicate) at index 80972, continuing at 81000
- Skipped scope entry (due to false predicate) at index 81001, continuing at 81029
- Match failed at index 80898
- Continuing at 81030
- Match failed at index 81033
- Continuing at 81137
- Match failed at index 81139
- Continuing at 81213
- Match failed at index 81216
- Continuing at 81334
- TypeSwitch[v16i8] from 81341 to 81358
- ISEL: Match complete!
- => Node40: v16i8 = bitcast Node8 [ID=15]
- Selecting: Node6: ch,glue = callseq_start Node0, i32 0 [ORD=4] [ID=13]
- ISEL: Starting pattern match on root node: Node6: ch,glue = callseq_start Node0, i32 0 [ORD=4] [ID=13]
- Initial Opcode index to 84589
- Morphed node: Node6: i32,ch,glue = ADJCALLSTACKDOWN32 i32 0, Node0 [ORD=4]
- ISEL: Match complete!
- => Node6: i32,ch,glue = ADJCALLSTACKDOWN32 i32 0, Node0 [ORD=4]
- Selecting: Node12: v4i32,ch = CopyFromReg Node0, Node11<reg %vreg1 [ORD=2] [ID=2]> [ORD=2] [ID=12]
- => Node12: v4i32,ch = CopyFromReg Node0, Node11<reg %vreg1 [ORD=2] [ID=2]> [ORD=2]
- Selecting: Node8: v4i32,ch = CopyFromReg Node0, Node7<reg %vreg0 [ORD=1] [ID=1]> [ORD=1] [ID=11]
- => Node8: v4i32,ch = CopyFromReg Node0, Node7<reg %vreg0 [ORD=1] [ID=1]> [ORD=1]
- Selecting: Node31: i32 = TargetConstantPool<<16 x i8> <i8 0, i8 4, i8 8, i8 12, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>> 0 [ID=10]
- => Node31: i32 = TargetConstantPool<<16 x i8> <i8 0, i8 4, i8 8, i8 12, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>> 0
- Selecting: Node18: Untyped = RegisterMask [ORD=4] [ID=6]
- => Node18: Untyped = RegisterMask [ORD=4]
- Selecting: Node17: i32 = TargetGlobalAddress<void (<16 x i8>)* @g> 0 [ORD=4] [ID=5]
- => Node17: i32 = TargetGlobalAddress<void (<16 x i8>)* @g> 0 [ORD=4]
- Selecting: Node5: v16i8 = Register %XMM0 [ORD=4] [ID=4]
- => Node5: v16i8 = Register %XMM0 [ORD=4]
- Selecting: Node4: i32 = TargetConstant<0> [ORD=4] [ID=3]
- => Node4: i32 = TargetConstant<0> [ORD=4]
- Selecting: Node11: v4i32 = Register %vreg1 [ORD=2] [ID=2]
- => Node11: v4i32 = Register %vreg1 [ORD=2]
- Selecting: Node7: v4i32 = Register %vreg0 [ORD=1] [ID=1]
- => Node7: v4i32 = Register %vreg0 [ORD=1]
- Selecting: Node0: ch = EntryToken [ORD=1] [ID=0]
- => Node0: ch = EntryToken [ORD=1]
- ===== Instruction selection ends:
- Selected selection DAG: BB#0 'f:'
- SelectionDAG has 25 nodes:
- Node0: ch = EntryToken [ORD=1]
- Node4: i32 = TargetConstant<0> [ORD=4]
- Node5: v16i8 = Register %XMM0 [ORD=4]
- Node39<reg %noreg>: <multiple use>
- Node3: i8 = TargetConstant<1>
- Node39<reg %noreg>: <multiple use>
- Node31: i32 = TargetConstantPool<<16 x i8> <i8 0, i8 4, i8 8, i8 12, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>> 0
- Node39<reg %noreg>: <multiple use>
- Node0: <multiple use>
- Node24: v2i64,ch = MOVAPSrm Node39<reg %noreg>, i8 1, Node39<reg %noreg>, Node31, Node39<reg %noreg>, Node0<Mem:LD16[ConstantPool]>
- Node0: <multiple use>
- Node7: v4i32 = Register %vreg0 [ORD=1]
- Node8: v4i32,ch = CopyFromReg Node0, Node7<reg %vreg0 [ORD=1]> [ORD=1]
- Node24: <multiple use>
- Node43: v16i8 = PSHUFBrr Node8, Node24
- i32 0: <multiple use>
- Node0: <multiple use>
- Node6: i32,ch,glue = ADJCALLSTACKDOWN32 i32 0, Node0 [ORD=4]
- Node5<reg %XMM0 [ORD=4]>: <multiple use>
- Node43: <multiple use>
- Node43: <multiple use>
- Node0: <multiple use>
- Node11: v4i32 = Register %vreg1 [ORD=2]
- Node12: v4i32,ch = CopyFromReg Node0, Node11<reg %vreg1 [ORD=2]> [ORD=2]
- Node24: <multiple use>
- Node34: v16i8 = PSHUFBrr Node12, Node24
- Node27: i32 = TargetConstant<9>
- Node21: f32 = COPY_TO_REGCLASS Node34, i32 9
- Node25: v4i32 = MOVSSrr Node43, Node21
- Node28: i8 = TargetConstant<36>
- Node38: v4i32 = SHUFPSrri Node43, Node25, i8 36
- Node16: ch,glue = CopyToReg Node6:1, Node5<reg %XMM0 [ORD=4]>, Node38 [ORD=4]
- Node17: i32 = TargetGlobalAddress<void (<16 x i8>)* @g> 0 [ORD=4]
- Node5<reg %XMM0 [ORD=4]>: <multiple use>
- Node18: Untyped = RegisterMask [ORD=4]
- Node16: <multiple use>
- Node16: <multiple use>
- Node19: ch,glue = CALLpcrel32 Node17, Node5<reg %XMM0 [ORD=4]>, Node18, Node16, Node16:1 [ORD=4]
- Node39: i32 = Register %noreg
- i32 0: <multiple use>
- i32 0: <multiple use>
- Node19: <multiple use>
- Node19: <multiple use>
- Node20: i32,ch,glue = ADJCALLSTACKUP32 i32 0, i32 0, Node19, Node19:1 [ORD=4]
- Node22: ch = RET Node20:1
- ********** List Scheduling BB#0 '' **********
- SU(0): Node22: ch = RET Node20:1 [ID=0]
- # preds left : 1
- # succs left : 0
- # rdefs left : 0
- Latency : 1
- Depth : 0
- Height : 0
- Predecessors:
- ch SU(1): Latency=1
- SU(1): Node20: i32,ch,glue = ADJCALLSTACKUP32 i32 0, i32 0, Node19, Node19:1 [ORD=4] [ID=1]
- Node16: ch,glue = CopyToReg Node6:1, Node5<reg %XMM0 [ORD=4]>, Node38 [ORD=4] [ID=1]
- Node19: ch,glue = CALLpcrel32 Node17, Node5<reg %XMM0 [ORD=4]>, Node18, Node16, Node16:1 [ORD=4] [ID=1]
- # preds left : 2
- # succs left : 1
- # rdefs left : 0
- Latency : 1
- Depth : 0
- Height : 0
- Predecessors:
- ch SU(10): Latency=1
- val SU(2): Latency=1
- Successors:
- ch SU(0): Latency=1
- SU(2): Node38: v4i32 = SHUFPSrri Node43, Node25, i8 36 [ID=2]
- # preds left : 2
- # succs left : 1
- # rdefs left : 1
- Latency : 1
- Depth : 0
- Height : 0
- Predecessors:
- val SU(8): Latency=1
- val SU(3): Latency=1
- Successors:
- val SU(1): Latency=1
- SU(3): Node25: v4i32 = MOVSSrr Node43, Node21 [ID=3]
- # preds left : 2
- # succs left : 1
- # rdefs left : 1
- Latency : 1
- Depth : 0
- Height : 0
- Predecessors:
- val SU(8): Latency=1
- val SU(4): Latency=1
- Successors:
- val SU(2): Latency=1
- SU(4): Node21: f32 = COPY_TO_REGCLASS Node34, i32 9 [ID=4]
- # preds left : 1
- # succs left : 1
- # rdefs left : 1
- Latency : 1
- Depth : 0
- Height : 0
- Predecessors:
- val SU(5): Latency=1
- Successors:
- val SU(3): Latency=1
- SU(5): Node34: v16i8 = PSHUFBrr Node12, Node24 [ID=5]
- # preds left : 2
- # succs left : 1
- # rdefs left : 1
- Latency : 1
- Depth : 0
- Height : 0
- Predecessors:
- val SU(7): Latency=1
- val SU(6): Latency=1
- Successors:
- val SU(4): Latency=1
- SU(6): Node24: v2i64,ch = MOVAPSrm Node39<reg %noreg>, i8 1, Node39<reg %noreg>, Node31, Node39<reg %noreg>, Node0<Mem:LD16[ConstantPool]> [ID=6]
- # preds left : 0
- # succs left : 2
- # rdefs left : 1
- Latency : 1
- Depth : 0
- Height : 0
- Successors:
- val SU(5): Latency=1
- val SU(8): Latency=1
- SU(7): Node12: v4i32,ch = CopyFromReg Node0, Node11<reg %vreg1 [ORD=2]> [ORD=2] [ID=7]
- # preds left : 0
- # succs left : 1
- # rdefs left : 1
- Latency : 1
- Depth : 0
- Height : 0
- Successors:
- val SU(5): Latency=1
- SU(8): Node43: v16i8 = PSHUFBrr Node8, Node24 [ID=8]
- # preds left : 2
- # succs left : 2
- # rdefs left : 1
- Latency : 1
- Depth : 0
- Height : 0
- Predecessors:
- val SU(9): Latency=1
- val SU(6): Latency=1
- Successors:
- val SU(2): Latency=1
- val SU(3): Latency=1
- SU(9): Node8: v4i32,ch = CopyFromReg Node0, Node7<reg %vreg0 [ORD=1]> [ORD=1] [ID=9]
- # preds left : 0
- # succs left : 1
- # rdefs left : 1
- Latency : 1
- Depth : 0
- Height : 0
- Successors:
- val SU(8): Latency=1
- SU(10): Node6: i32,ch,glue = ADJCALLSTACKDOWN32 i32 0, Node0 [ORD=4] [ID=10]
- # preds left : 0
- # succs left : 1
- # rdefs left : 0
- Latency : 1
- Depth : 0
- Height : 0
- Successors:
- ch SU(1): Latency=1
- Examining Available:
- Height 0: SU(0): Node22: ch = RET Node20:1 [ID=0]
- *** Scheduling [0]: SU(0): Node22: ch = RET Node20:1 [ID=0]
- Examining Available:
- Height 1: SU(1): Node20: i32,ch,glue = ADJCALLSTACKUP32 i32 0, i32 0, Node19, Node19:1 [ORD=4] [ID=1]
- Node16: ch,glue = CopyToReg Node6:1, Node5<reg %XMM0 [ORD=4]>, Node38 [ORD=4] [ID=1]
- Node19: ch,glue = CALLpcrel32 Node17, Node5<reg %XMM0 [ORD=4]>, Node18, Node16, Node16:1 [ORD=4] [ID=1]
- *** Scheduling [1]: SU(1): Node20: i32,ch,glue = ADJCALLSTACKUP32 i32 0, i32 0, Node19, Node19:1 [ORD=4] [ID=1]
- Node16: ch,glue = CopyToReg Node6:1, Node5<reg %XMM0 [ORD=4]>, Node38 [ORD=4] [ID=1]
- Node19: ch,glue = CALLpcrel32 Node17, Node5<reg %XMM0 [ORD=4]>, Node18, Node16, Node16:1 [ORD=4] [ID=1]
- Examining Available:
- Height 2: SU(10): Node6: i32,ch,glue = ADJCALLSTACKDOWN32 i32 0, Node0 [ORD=4] [ID=10]
- Height 2: SU(2): Node38: v4i32 = SHUFPSrri Node43, Node25, i8 36 [ID=2]
- *** Scheduling [2]: SU(10): Node6: i32,ch,glue = ADJCALLSTACKDOWN32 i32 0, Node0 [ORD=4] [ID=10]
- Examining Available:
- Height 2: SU(2): Node38: v4i32 = SHUFPSrri Node43, Node25, i8 36 [ID=2]
- *** Scheduling [3]: SU(2): Node38: v4i32 = SHUFPSrri Node43, Node25, i8 36 [ID=2]
- Examining Available:
- Height 4: SU(3): Node25: v4i32 = MOVSSrr Node43, Node21 [ID=3]
- *** Scheduling [4]: SU(3): Node25: v4i32 = MOVSSrr Node43, Node21 [ID=3]
- Examining Available:
- Height 5: SU(4): Node21: f32 = COPY_TO_REGCLASS Node34, i32 9 [ID=4]
- Height 5: SU(8): Node43: v16i8 = PSHUFBrr Node8, Node24 [ID=8]
- *** Scheduling [5]: SU(4): Node21: f32 = COPY_TO_REGCLASS Node34, i32 9 [ID=4]
- Examining Available:
- Height 6: SU(5): Node34: v16i8 = PSHUFBrr Node12, Node24 [ID=5]
- Height 5: SU(8): Node43: v16i8 = PSHUFBrr Node8, Node24 [ID=8]
- *** Scheduling [6]: SU(5): Node34: v16i8 = PSHUFBrr Node12, Node24 [ID=5]
- Examining Available:
- Height 7: SU(7): Node12: v4i32,ch = CopyFromReg Node0, Node11<reg %vreg1 [ORD=2]> [ORD=2] [ID=7]
- Height 5: SU(8): Node43: v16i8 = PSHUFBrr Node8, Node24 [ID=8]
- *** Scheduling [7]: SU(7): Node12: v4i32,ch = CopyFromReg Node0, Node11<reg %vreg1 [ORD=2]> [ORD=2] [ID=7]
- Examining Available:
- Height 5: SU(8): Node43: v16i8 = PSHUFBrr Node8, Node24 [ID=8]
- *** Scheduling [8]: SU(8): Node43: v16i8 = PSHUFBrr Node8, Node24 [ID=8]
- Examining Available:
- Height 9: SU(9): Node8: v4i32,ch = CopyFromReg Node0, Node7<reg %vreg0 [ORD=1]> [ORD=1] [ID=9]
- Height 9: SU(6): Node24: v2i64,ch = MOVAPSrm Node39<reg %noreg>, i8 1, Node39<reg %noreg>, Node31, Node39<reg %noreg>, Node0<Mem:LD16[ConstantPool]> [ID=6]
- *** Scheduling [9]: SU(9): Node8: v4i32,ch = CopyFromReg Node0, Node7<reg %vreg0 [ORD=1]> [ORD=1] [ID=9]
- Examining Available:
- Height 9: SU(6): Node24: v2i64,ch = MOVAPSrm Node39<reg %noreg>, i8 1, Node39<reg %noreg>, Node31, Node39<reg %noreg>, Node0<Mem:LD16[ConstantPool]> [ID=6]
- *** Scheduling [10]: SU(6): Node24: v2i64,ch = MOVAPSrm Node39<reg %noreg>, i8 1, Node39<reg %noreg>, Node31, Node39<reg %noreg>, Node0<Mem:LD16[ConstantPool]> [ID=6]
- *** Final schedule ***
- SU(6): Node24: v2i64,ch = MOVAPSrm Node39<reg %noreg>, i8 1, Node39<reg %noreg>, Node31, Node39<reg %noreg>, Node0<Mem:LD16[ConstantPool]> [ID=6]
- SU(9): Node8: v4i32,ch = CopyFromReg Node0, Node7<reg %vreg0 [ORD=1]> [ORD=1] [ID=9]
- SU(8): Node43: v16i8 = PSHUFBrr Node8, Node24 [ID=8]
- SU(7): Node12: v4i32,ch = CopyFromReg Node0, Node11<reg %vreg1 [ORD=2]> [ORD=2] [ID=7]
- SU(5): Node34: v16i8 = PSHUFBrr Node12, Node24 [ID=5]
- SU(4): Node21: f32 = COPY_TO_REGCLASS Node34, i32 9 [ID=4]
- SU(3): Node25: v4i32 = MOVSSrr Node43, Node21 [ID=3]
- SU(2): Node38: v4i32 = SHUFPSrri Node43, Node25, i8 36 [ID=2]
- SU(10): Node6: i32,ch,glue = ADJCALLSTACKDOWN32 i32 0, Node0 [ORD=4] [ID=10]
- SU(1): Node20: i32,ch,glue = ADJCALLSTACKUP32 i32 0, i32 0, Node19, Node19:1 [ORD=4] [ID=1]
- Node16: ch,glue = CopyToReg Node6:1, Node5<reg %XMM0 [ORD=4]>, Node38 [ORD=4] [ID=1]
- Node19: ch,glue = CALLpcrel32 Node17, Node5<reg %XMM0 [ORD=4]>, Node18, Node16, Node16:1 [ORD=4] [ID=1]
- SU(0): Node22: ch = RET Node20:1 [ID=0]
- Total amount of phi nodes to update: 0
- # Machine code for function f: SSA
- Constant Pool:
- cp#0: <16 x i8> <i8 0, i8 4, i8 8, i8 12, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, align=16
- Function Live Ins: %XMM0 in %vreg0, %XMM1 in %vreg1
- 0B BB#0: derived from LLVM BB %0
- Live Ins: %XMM0 %XMM1
- 16B %vreg1<def> = COPY %XMM1; VR128:%vreg1
- 32B %vreg0<def> = COPY %XMM0; VR128:%vreg0
- 48B %vreg2<def> = MOVAPSrm %noreg, 1, %noreg, <cp#0>, %noreg; mem:LD16[ConstantPool] VR128:%vreg2
- 64B %vreg3<def,tied1> = PSHUFBrr %vreg0<tied0>, %vreg2; VR128:%vreg3,%vreg0,%vreg2
- 80B %vreg4<def,tied1> = PSHUFBrr %vreg1<tied0>, %vreg2; VR128:%vreg4,%vreg1,%vreg2
- 96B %vreg5<def> = COPY %vreg4; FR32:%vreg5 VR128:%vreg4
- 112B %vreg6<def,tied1> = MOVSSrr %vreg3<tied0>, %vreg5<kill>; VR128:%vreg6,%vreg3 FR32:%vreg5
- 128B %vreg7<def,tied1> = SHUFPSrri %vreg3<tied0>, %vreg6<kill>, 36; VR128:%vreg7,%vreg3,%vreg6
- 144B ADJCALLSTACKDOWN32 0, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
- 160B %XMM0<def> = COPY %vreg7; VR128:%vreg7
- 176B CALLpcrel32 <ga:@g>, <regmask>, %ESP<imp-use>, %XMM0<imp-use>, %ESP<imp-def>
- 192B ADJCALLSTACKUP32 0, 0, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
- 208B RET
- # End machine code for function f.
- ********** Stack Coloring **********
- ********** Function: f
- ******** Pre-regalloc Machine LICM: f ********
- Entering:
- Coalescing: %vreg5<def> = COPY %vreg4; FR32:%vreg5 VR128:%vreg4
- *** to: %vreg6<def,tied1> = MOVSSrr %vreg3<tied0>, %vreg5<kill>; VR128:%vreg6,%vreg3 FR32:%vreg5
- Exiting:
- ******** Machine Sinking ********
- ********** PROCESS IMPLICIT DEFS **********
- ********** Function: f
- ********** REWRITING TWO-ADDR INSTRS **********
- ********** Function: f
- %vreg3<def,tied1> = PSHUFBrr %vreg0<kill,tied0>, %vreg2; VR128:%vreg3,%vreg0,%vreg2
- prepend: %vreg3<def> = COPY %vreg0; VR128:%vreg3,%vreg0
- rewrite to: %vreg3<def,tied1> = PSHUFBrr %vreg3<tied0>, %vreg2; VR128:%vreg3,%vreg2
- %vreg4<def,tied1> = PSHUFBrr %vreg1<kill,tied0>, %vreg2<kill>; VR128:%vreg4,%vreg1,%vreg2
- prepend: %vreg4<def> = COPY %vreg1; VR128:%vreg4,%vreg1
- rewrite to: %vreg4<def,tied1> = PSHUFBrr %vreg4<tied0>, %vreg2<kill>; VR128:%vreg4,%vreg2
- %vreg6<def,tied1> = MOVSSrr %vreg3<tied0>, %vreg4<kill>; VR128:%vreg6,%vreg3,%vreg4
- prepend: %vreg6<def> = COPY %vreg3; VR128:%vreg6,%vreg3
- rewrite to: %vreg6<def,tied1> = MOVSSrr %vreg6<tied0>, %vreg4<kill>; VR128:%vreg6,%vreg4
- %vreg7<def,tied1> = SHUFPSrri %vreg3<kill,tied0>, %vreg6<kill>, 36; VR128:%vreg7,%vreg3,%vreg6
- prepend: %vreg7<def> = COPY %vreg3; VR128:%vreg7,%vreg3
- rewrite to: %vreg7<def,tied1> = SHUFPSrri %vreg7<tied0>, %vreg6<kill>, 36; VR128:%vreg7,%vreg6
- # Machine code for function f: Post SSA
- Constant Pool:
- cp#0: <16 x i8> <i8 0, i8 4, i8 8, i8 12, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, align=16
- Function Live Ins: %XMM0 in %vreg0, %XMM1 in %vreg1
- 0B BB#0: derived from LLVM BB %0
- Live Ins: %XMM0 %XMM1
- 16B %vreg1<def> = COPY %XMM1<kill>; VR128:%vreg1
- 32B %vreg0<def> = COPY %XMM0<kill>; VR128:%vreg0
- 48B %vreg2<def> = MOVAPSrm %noreg, 1, %noreg, <cp#0>, %noreg; mem:LD16[ConstantPool] VR128:%vreg2
- 64B %vreg3<def> = COPY %vreg0<kill>; VR128:%vreg3,%vreg0
- 80B %vreg3<def,tied1> = PSHUFBrr %vreg3<tied0>, %vreg2; VR128:%vreg3,%vreg2
- 96B %vreg4<def> = COPY %vreg1<kill>; VR128:%vreg4,%vreg1
- 112B %vreg4<def,tied1> = PSHUFBrr %vreg4<tied0>, %vreg2<kill>; VR128:%vreg4,%vreg2
- 128B %vreg6<def> = COPY %vreg3; VR128:%vreg6,%vreg3
- 144B %vreg6<def,tied1> = MOVSSrr %vreg6<tied0>, %vreg4<kill>; VR128:%vreg6,%vreg4
- 160B %vreg7<def> = COPY %vreg3<kill>; VR128:%vreg7,%vreg3
- 176B %vreg7<def,tied1> = SHUFPSrri %vreg7<tied0>, %vreg6<kill>, 36; VR128:%vreg7,%vreg6
- 192B ADJCALLSTACKDOWN32 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
- 208B %XMM0<def> = COPY %vreg7<kill>; VR128:%vreg7
- 224B CALLpcrel32 <ga:@g>, <regmask>, %ESP<imp-use>, %XMM0<imp-use,kill>, %ESP<imp-def>
- 240B ADJCALLSTACKUP32 0, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
- 256B RET
- # End machine code for function f.
- ********** COMPUTING LIVE INTERVALS **********
- ********** Function: f
- BB#0: # derived from
- 16B %vreg1<def> = COPY %XMM1<kill>; VR128:%vreg1
- register: %vreg1 +[16r,96r:0)
- 32B %vreg0<def> = COPY %XMM0<kill>; VR128:%vreg0
- register: %vreg0 +[32r,64r:0)
- 48B %vreg2<def> = MOVAPSrm %noreg, 1, %noreg, <cp#0>, %noreg; mem:LD16[ConstantPool] VR128:%vreg2
- register: %vreg2 +[48r,112r:0)
- 64B %vreg3<def> = COPY %vreg0<kill>; VR128:%vreg3,%vreg0
- register: %vreg3 +[64r,160r:0)
- 80B %vreg3<def,tied1> = PSHUFBrr %vreg3<tied0>, %vreg2; VR128:%vreg3,%vreg2
- register: %vreg3 replace range with [64r,80r:1) RESULT: [64r,80r:1)[80r,160r:0) 0@80r 1@64r
- 96B %vreg4<def> = COPY %vreg1<kill>; VR128:%vreg4,%vreg1
- register: %vreg4 +[96r,144r:0)
- 112B %vreg4<def,tied1> = PSHUFBrr %vreg4<tied0>, %vreg2<kill>; VR128:%vreg4,%vreg2
- register: %vreg4 replace range with [96r,112r:1) RESULT: [96r,112r:1)[112r,144r:0) 0@112r 1@96r
- 128B %vreg6<def> = COPY %vreg3; VR128:%vreg6,%vreg3
- register: %vreg6 +[128r,176r:0)
- 144B %vreg6<def,tied1> = MOVSSrr %vreg6<tied0>, %vreg4<kill>; VR128:%vreg6,%vreg4
- register: %vreg6 replace range with [128r,144r:1) RESULT: [128r,144r:1)[144r,176r:0) 0@144r 1@128r
- 160B %vreg7<def> = COPY %vreg3<kill>; VR128:%vreg7,%vreg3
- register: %vreg7 +[160r,208r:0)
- 176B %vreg7<def,tied1> = SHUFPSrri %vreg7<tied0>, %vreg6<kill>, 36; VR128:%vreg7,%vreg6
- register: %vreg7 replace range with [160r,176r:1) RESULT: [160r,176r:1)[176r,208r:0) 0@176r 1@160r
- 192B ADJCALLSTACKDOWN32 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
- 208B %XMM0<def> = COPY %vreg7<kill>; VR128:%vreg7
- 224B CALLpcrel32 <ga:@g>, <regmask>, %ESP<imp-use>, %XMM0<imp-use,kill>, %ESP<imp-def>
- 240B ADJCALLSTACKUP32 0, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
- 256B RET
- Computing live-in reg-units in ABI blocks.
- 0B BB#0 XMM0#0 XMM1#0
- Created 2 new intervals.
- ********** INTERVALS **********
- XMM0 = [0B,32r:0)[208r,224r:1) 0@0B-phi 1@208r
- XMM1 = [0B,16r:0) 0@0B-phi
- %vreg0 = [32r,64r:0) 0@32r
- %vreg1 = [16r,96r:0) 0@16r
- %vreg2 = [48r,112r:0) 0@48r
- %vreg3 = [64r,80r:1)[80r,160r:0) 0@80r 1@64r
- %vreg4 = [96r,112r:1)[112r,144r:0) 0@112r 1@96r
- %vreg6 = [128r,144r:1)[144r,176r:0) 0@144r 1@128r
- %vreg7 = [160r,176r:1)[176r,208r:0) 0@176r 1@160r
- ********** MACHINEINSTRS **********
- # Machine code for function f: Post SSA
- Constant Pool:
- cp#0: <16 x i8> <i8 0, i8 4, i8 8, i8 12, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, align=16
- Function Live Ins: %XMM0 in %vreg0, %XMM1 in %vreg1
- 0B BB#0: derived from LLVM BB %0
- Live Ins: %XMM0 %XMM1
- 16B %vreg1<def> = COPY %XMM1; VR128:%vreg1
- 32B %vreg0<def> = COPY %XMM0; VR128:%vreg0
- 48B %vreg2<def> = MOVAPSrm %noreg, 1, %noreg, <cp#0>, %noreg; mem:LD16[ConstantPool] VR128:%vreg2
- 64B %vreg3<def> = COPY %vreg0<kill>; VR128:%vreg3,%vreg0
- 80B %vreg3<def,tied1> = PSHUFBrr %vreg3<tied0>, %vreg2; VR128:%vreg3,%vreg2
- 96B %vreg4<def> = COPY %vreg1<kill>; VR128:%vreg4,%vreg1
- 112B %vreg4<def,tied1> = PSHUFBrr %vreg4<tied0>, %vreg2<kill>; VR128:%vreg4,%vreg2
- 128B %vreg6<def> = COPY %vreg3; VR128:%vreg6,%vreg3
- 144B %vreg6<def,tied1> = MOVSSrr %vreg6<tied0>, %vreg4<kill>; VR128:%vreg6,%vreg4
- 160B %vreg7<def> = COPY %vreg3<kill>; VR128:%vreg7,%vreg3
- 176B %vreg7<def,tied1> = SHUFPSrri %vreg7<tied0>, %vreg6<kill>, 36; VR128:%vreg7,%vreg6
- 192B ADJCALLSTACKDOWN32 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
- 208B %XMM0<def> = COPY %vreg7<kill>; VR128:%vreg7
- 224B CALLpcrel32 <ga:@g>, <regmask>, %ESP<imp-use>, %XMM0<imp-use>, %ESP<imp-def>
- 240B ADJCALLSTACKUP32 0, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
- 256B RET
- # End machine code for function f.
- ********** COMPUTING LIVE DEBUG VARIABLES: f **********
- ********** DEBUG VARIABLES **********
- ********** SIMPLE REGISTER COALESCING **********
- ********** Function: f
- ********** JOINING INTERVALS ***********
- :
- 16B %vreg1<def> = COPY %XMM1; VR128:%vreg1
- Considering merging %vreg1 with %XMM1
- Can only merge into reserved registers.
- 32B %vreg0<def> = COPY %XMM0; VR128:%vreg0
- Considering merging %vreg0 with %XMM0
- Can only merge into reserved registers.
- 64B %vreg3<def> = COPY %vreg0<kill>; VR128:%vreg3,%vreg0
- Considering merging to VR128 with %vreg0 in %vreg3
- RHS = %vreg0 [32r,64r:0) 0@32r
- LHS = %vreg3 [64r,80r:1)[80r,160r:0) 0@80r 1@64r
- erased: 64B %vreg3<def> = COPY %vreg0<kill>; VR128:%vreg3,%vreg0
- AllocationOrder(VR128) = [ %XMM0 %XMM1 %XMM2 %XMM3 %XMM4 %XMM5 %XMM6 %XMM7 ]
- updated: 32B %vreg3<def> = COPY %XMM0; VR128:%vreg3
- Joined. Result = %vreg3[32r,80r:1)[80r,160r:0) 0@80r 1@32r
- 96B %vreg4<def> = COPY %vreg1<kill>; VR128:%vreg4,%vreg1
- Considering merging to VR128 with %vreg1 in %vreg4
- RHS = %vreg1 [16r,96r:0) 0@16r
- LHS = %vreg4 [96r,112r:1)[112r,144r:0) 0@112r 1@96r
- erased: 96B %vreg4<def> = COPY %vreg1<kill>; VR128:%vreg4,%vreg1
- updated: 16B %vreg4<def> = COPY %XMM1; VR128:%vreg4
- Joined. Result = %vreg4[16r,112r:1)[112r,144r:0) 0@112r 1@16r
- 128B %vreg6<def> = COPY %vreg3; VR128:%vreg6,%vreg3
- Considering merging to VR128 with %vreg3 in %vreg6
- RHS = %vreg3 [32r,80r:1)[80r,160r:0) 0@80r 1@32r
- LHS = %vreg6 [128r,144r:1)[144r,176r:0) 0@144r 1@128r
- Interference!
- 160B %vreg7<def> = COPY %vreg3<kill>; VR128:%vreg7,%vreg3
- Considering merging to VR128 with %vreg3 in %vreg7
- RHS = %vreg3 [32r,80r:1)[80r,160r:0) 0@80r 1@32r
- LHS = %vreg7 [160r,176r:1)[176r,208r:0) 0@176r 1@160r
- erased: 160B %vreg7<def> = COPY %vreg3<kill>; VR128:%vreg7,%vreg3
- updated: 32B %vreg7<def> = COPY %XMM0; VR128:%vreg7
- updated: 80B %vreg7<def,tied1> = PSHUFBrr %vreg7<tied0>, %vreg2; VR128:%vreg7,%vreg2
- updated: 128B %vreg6<def> = COPY %vreg7; VR128:%vreg6,%vreg7
- Joined. Result = %vreg7[32r,80r:2)[80r,176r:1)[176r,208r:0) 0@176r 1@80r 2@32r
- 208B %XMM0<def> = COPY %vreg7<kill>; VR128:%vreg7
- Considering merging %vreg7 with %XMM0
- Can only merge into reserved registers.
- 128B %vreg6<def> = COPY %vreg7; VR128:%vreg6,%vreg7
- Considering merging to VR128 with %vreg7 in %vreg6
- RHS = %vreg6 [128r,144r:1)[144r,176r:0) 0@144r 1@128r
- LHS = %vreg7 [32r,80r:2)[80r,176r:1)[176r,208r:0) 0@176r 1@80r 2@32r
- Interference!
- Trying to inflate 0 regs.
- ********** INTERVALS **********
- XMM0 = [0B,32r:0)[208r,224r:1) 0@0B-phi 1@208r
- XMM1 = [0B,16r:0) 0@0B-phi
- %vreg2 = [48r,112r:0) 0@48r
- %vreg4 = [16r,112r:1)[112r,144r:0) 0@112r 1@16r
- %vreg6 = [128r,144r:1)[144r,176r:0) 0@144r 1@128r
- %vreg7 = [32r,80r:2)[80r,176r:1)[176r,208r:0) 0@176r 1@80r 2@32r
- ********** MACHINEINSTRS **********
- # Machine code for function f: Post SSA
- Constant Pool:
- cp#0: <16 x i8> <i8 0, i8 4, i8 8, i8 12, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, align=16
- Function Live Ins: %XMM0 in %vreg0, %XMM1 in %vreg1
- 0B BB#0: derived from LLVM BB %0
- Live Ins: %XMM0 %XMM1
- 16B %vreg4<def> = COPY %XMM1; VR128:%vreg4
- 32B %vreg7<def> = COPY %XMM0; VR128:%vreg7
- 48B %vreg2<def> = MOVAPSrm %noreg, 1, %noreg, <cp#0>, %noreg; mem:LD16[ConstantPool] VR128:%vreg2
- 80B %vreg7<def,tied1> = PSHUFBrr %vreg7<tied0>, %vreg2; VR128:%vreg7,%vreg2
- 112B %vreg4<def,tied1> = PSHUFBrr %vreg4<tied0>, %vreg2<kill>; VR128:%vreg4,%vreg2
- 128B %vreg6<def> = COPY %vreg7; VR128:%vreg6,%vreg7
- 144B %vreg6<def,tied1> = MOVSSrr %vreg6<tied0>, %vreg4<kill>; VR128:%vreg6,%vreg4
- 176B %vreg7<def,tied1> = SHUFPSrri %vreg7<tied0>, %vreg6<kill>, 36; VR128:%vreg7,%vreg6
- 192B ADJCALLSTACKDOWN32 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
- 208B %XMM0<def> = COPY %vreg7<kill>; VR128:%vreg7
- 224B CALLpcrel32 <ga:@g>, <regmask>, %ESP<imp-use>, %XMM0<imp-use>, %ESP<imp-def>
- 240B ADJCALLSTACKUP32 0, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
- 256B RET
- # End machine code for function f.
- ********** DEBUG VARIABLES **********
- ********** Compute Spill Weights **********
- ********** Function: f
- ********** GREEDY REGISTER ALLOCATION **********
- ********** Function: f
- selectOrSplit VR128:%vreg7 [32r,80r:2)[80r,176r:1)[176r,208r:0) 0@176r 1@80r 2@32r
- AllocationOrder(VR128) = [ %XMM0 %XMM1 %XMM2 %XMM3 %XMM4 %XMM5 %XMM6 %XMM7 ]
- assigning %vreg7 to %XMM0: XMM0
- selectOrSplit VR128:%vreg4 [16r,112r:1)[112r,144r:0) 0@112r 1@16r
- assigning %vreg4 to %XMM1: XMM1
- selectOrSplit VR128:%vreg2 [48r,112r:0) 0@48r
- assigning %vreg2 to %XMM2: XMM2
- selectOrSplit VR128:%vreg6 [128r,144r:1)[144r,176r:0) 0@144r 1@128r
- assigning %vreg6 to %XMM2: XMM2
- ********** REWRITE VIRTUAL REGISTERS **********
- ********** Function: f
- ********** REGISTER MAP **********
- [%vreg2 -> %XMM2] VR128
- [%vreg4 -> %XMM1] VR128
- [%vreg6 -> %XMM2] VR128
- [%vreg7 -> %XMM0] VR128
- 0B BB#0: derived from LLVM BB %0
- Live Ins: %XMM0 %XMM1
- 16B %vreg4<def> = COPY %XMM1; VR128:%vreg4
- 32B %vreg7<def> = COPY %XMM0; VR128:%vreg7
- 48B %vreg2<def> = MOVAPSrm %noreg, 1, %noreg, <cp#0>, %noreg; mem:LD16[ConstantPool] VR128:%vreg2
- 80B %vreg7<def,tied1> = PSHUFBrr %vreg7<kill,tied0>, %vreg2; VR128:%vreg7,%vreg2
- 112B %vreg4<def,tied1> = PSHUFBrr %vreg4<kill,tied0>, %vreg2<kill>; VR128:%vreg4,%vreg2
- 128B %vreg6<def> = COPY %vreg7; VR128:%vreg6,%vreg7
- 144B %vreg6<def,tied1> = MOVSSrr %vreg6<kill,tied0>, %vreg4<kill>; VR128:%vreg6,%vreg4
- 176B %vreg7<def,tied1> = SHUFPSrri %vreg7<kill,tied0>, %vreg6<kill>, 36; VR128:%vreg7,%vreg6
- 192B ADJCALLSTACKDOWN32 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
- 208B %XMM0<def> = COPY %vreg7<kill>; VR128:%vreg7
- 224B CALLpcrel32 <ga:@g>, <regmask>, %ESP<imp-use>, %XMM0<imp-use>, %ESP<imp-def>
- 240B ADJCALLSTACKUP32 0, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
- 256B RET
- > %XMM1<def> = COPY %XMM1
- Deleting identity copy.
- > %XMM0<def> = COPY %XMM0
- Deleting identity copy.
- > %XMM2<def> = MOVAPSrm %noreg, 1, %noreg, <cp#0>, %noreg; mem:LD16[ConstantPool]
- > %XMM0<def,tied1> = PSHUFBrr %XMM0<kill,tied0>, %XMM2
- > %XMM1<def,tied1> = PSHUFBrr %XMM1<kill,tied0>, %XMM2<kill>
- > %XMM2<def> = COPY %XMM0
- > %XMM2<def,tied1> = MOVSSrr %XMM2<kill,tied0>, %XMM1<kill>
- > %XMM0<def,tied1> = SHUFPSrri %XMM0<kill,tied0>, %XMM2<kill>, 36
- > ADJCALLSTACKDOWN32 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
- > %XMM0<def> = COPY %XMM0<kill>
- Deleting identity copy.
- > CALLpcrel32 <ga:@g>, <regmask>, %ESP<imp-use>, %XMM0<imp-use>, %ESP<imp-def>
- > ADJCALLSTACKUP32 0, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
- > RET
- ********** EMITTING LIVE DEBUG VARIABLES **********
- ********** Stack Slot Coloring **********
- ********** Function: f
- ******** Post-regalloc Machine LICM: f ********
- Setting up live-ins for BB#0 derived from .
- Block has no FP live-ins.
- FPInst: RET
- Stack contents:
- Inserted instructions:
- RET
- Stack contents:
- Machine Function
- ********** EXPANDING POST-RA PSEUDO INSTRS **********
- ********** Function: f
- real copy: %XMM2<def> = COPY %XMM0
- replaced by: %XMM2<def> = MOVAPSrr %XMM0
- RPO[BB#0 derived from LLVM BB ] = 1
- POT: BB#0 derived from LLVM BB
- doLoop(BB#0 derived from LLVM BB , BB#0 derived from LLVM BB )
- doBlock(BB#0 derived from LLVM BB )
- Frequency(BB#0 derived from LLVM BB ) = 0
- Frequency(BB#0 derived from LLVM BB ) = 1024
- ********** FIX EXECUTION DEPENDENCIES: VR128 **********
- BB#0: entry
- XMM2: 2 %XMM2<def> = MOVAPSrm %noreg, 1, %noreg, <cp#0>, %noreg; mem:LD16[ConstantPool]
- XMM0: 3 %XMM0<def,tied1> = PSHUFBrr %XMM0<kill,tied0>, %XMM2
- XMM1: 4 %XMM1<def,tied1> = PSHUFBrr %XMM1<kill,tied0>, %XMM2<kill>
- XMM2: 5 %XMM2<def> = MOVDQArr %XMM0
- XMM2: 6 %XMM2<def,tied1> = MOVSSrr %XMM2<kill,tied0>, %XMM1<kill>
- XMM0: 7 %XMM0<def,tied1> = SHUFPSrri %XMM0<kill,tied0>, %XMM2<kill>, 36
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