Link Register used for similar functions + ButtonedBlinky

            TTL Blinky
            AREA Myprog,CODE,READONLY
            ENTRY
            EXPORT __main
            ;Some Notes for the STM32F401RE NUCLEO Board
            ;NB Onboard LED is PA5 and User Button is PC13
            ;Setup Registers as follows
            ;
            ;RCC_AHB1ENR Peripheral clock enable register THIS NEEDS TO BE ENABLED FIRST before changing GPIOx as below!
            ;
            ;GPIOA_MODER
            ;GPIOA_OTYPER
            ;GPIOA_SPEEDR
            ;GPIOA_PUPDR
            ;
            ;Data Registers as follows (All 32bit Registers)
            ;GPIOA_IDR  (Input)
            ;GPIOA_ODR  (Output)
            ;GPIOA_BSRR (Set/Reset)
            ;GPIOA_LCKR (Locking)
            ;GPIOA_AFRH (Alternate function Selection High 32bit Word)
            ;GPIOA_AFRL (Alternate function Selection Low  32bit Word)

__main      ;Notes for the Following M.R.Simpson November 2015
            ; (+ some bits by R.Merrison-Hort February 2016)
            ;Your Initialization code could go here e.g. Clearing Regsiters setup IO etc.,
            ;Note This is a very simple Program 'blinky'

setupIO     LDR R0,=0x40023800      ;Load Address in R0 i.e. RCC REG Base Address (offset 0x30 for GPIO Clock Enable Register (RCC_AHB1ENBR)) Page 114 RM0368
            LDR R1,[R0, #0x30]      ;Load R1 with contents of Address in R0 offset by 0x30 i.e. RCC_AHB1ENR
            MOV R2,#5               ;Move a 5 into R2 to enable clock for ports A and C.
            ORR R1,R2               ;Set the bit as above using OR function and store in R1
            STR R1,[R0, #0x30]      ;Store R1 into Address in R0 offset by 0x30 i.e. RCC REG Base Address offset 0x30 for GPIO Clock EN (AHB1)

            LDR R0,=0x40020000      ;GPIOA Base Address in R0 Page 38 RM0368

            LDR R1,[R0, #0x00]      ;MODER Offset by 0x00 Page 151 RM0368
            MOV R2,#1               ;Setting GPIOA Bit 10 which is PA5 on the Nucleo Board i.e.Onboard LED
            LSL R2,#10              ;  using in 'c' terms
            ORR R1,R2               ;   'R1=R1|(1<<10)'
            STR R1,[R0, #0x00]      ;Store R1 in Address in R0 offset by 0x00 i.e. MODER REG

            LDR R1,[R0, #0x08]      ;OSPEEDR Offset by 0x08 Page 152 RM0368
            MOV R2,#00              ;Setting OSPEEDR Bits 11:10 which is PA5 on the Nucleo Board i.e.Onboard LED to 0:0 slow, 0:1 medium, 1:0 fast, 1:1 high
            LSL R2,#10              ;  using in 'c' terms
            ORR R1,R2               ;   'R1=R1|(1<<10)'
            STR R1,[R0, #0x08]      ;Store R1 in Address in R0 offset by 0x00 i.e. MODER REG

            LDR R5,=0x40020800      ;GPIOC Base Address in R5 Page 38 RM0368
            LDR R1,[R5, #0x08]      ;Set P13 as input mode (should be the case at startup anyway).
            BIC R1, #0xC000000
            STR R1,[R5, #0x08]


loopy       LDR R7, [R5, #0x10]
            AND R7, R7, 0x2000
            CMP R7, #0
            BNE loopy
            ;LED ON
            LDR R1,[R0, #0x14]      ;LOAD the contents of ODR offset by 0x14 into R1 referance Page 155 RM0368
            MOV R2,#1               ;1 of 3 lines to do a 'R1=R1|(1<<5)'
            LSL R2,#5               ;2 of 3 lines to do a 'R1=R1|(1<<5)'
            ORR R1,R2               ;3 of 3 lines to do a 'R1=R1|(1<<5)'
            STR R1,[R0,#0x14]       ;STORE the contents of R1 back into the ODR offset by 0x14 Page 155 RM0368

            ;DELAY Load R6 with the number of milliseconds to wait (500)
            BL delayStart

            ;LED OFF
            LDR R1,[R0, #0x14]      ;LOAD the contents of ODR offset by 0x14 into R1 referance Page 155 RM0368
            MOV R2,#1               ;1 of 3 lines to do a 'R1=R1|1<<5' note: 1 = a bit to manipulate
            LSL R2,#5               ;2 of 3 lines to do a 'R1=R1|1<<5' note: 5 = num places to move
            BIC R1,R2               ;3 of 3 lines to do a 'R1=R1&~(1<<5)' note: push down the 5th (r2) bit to 0
            STR R1,[R0,#0x14]       ;STORE the contents of R1 back into the ODR offset by 0x14 Page 155 RM0368

            ;DELAY Load R6 with the number of milliseconds to wait (500)
            BL delayStart

            B   loopy               ;Branch to loopy (Forever...)

                                    ;This is just a Blocking Method
                                    ;1,600,000 each Instruction is 84MHz=11.9ns 1600000*21(instructions 1+1+1+18(Stack))=500ms

            BX  LR          ;1+P    ;Return to address Stored in LR (Link Register)

delayStart  MOV R6,#500  ; Start of outer loop, counts down from 500
delay       MOV R7,#3200 ; Start of inner loop, counts down from 3200 (takes ~1ms)
delayi      SUB R7,#0x01
            CMP R7,#0x00
            BNE delayi
            SUB R6,#1
            CMP R6,#0
            BNE delay
            BX lr

            END                     ;Inform Compiler this is end of the Coding