logic [2:0] n, nD;
logic [3:0] b, bD;
logic [7:0] a, p, pa, aD, pD, yD;
logic doneD;

always_ff (@posedge CLK) n <= nD;
always_ff (@posedge CLK) b <= bD;
always_ff (@posedge CLK) a <= aD;
always_ff (@posedge CLK) p <= pD;
always_ff (@posedge CLK) DONE <= doneD;
always_ff (@posedge CLK) Y <= yD;

assign nD= RST ? 0 : START ? 4 : n>0 ? n-1 : 0;
assign bD= RST ? 0 : START ? B :  b >> 1;
assign aD= RST ? 0 : START ? A :  a << 1;
assign pD= RST ? 0 : START ? 0 :  b[0] ? p+a: p;
assign doneD= n==1 ? 1 : 0;
assign yD= RST ? 0 : n==0 ? pD;

endmodule