Exam tips 411

Run hw2 in pipeline simulator. Look at hazards/stalls
Study little's law

Parallelism: pipelines, concurrency, bandwidth, latency


(64) Pipelined control: Multiple pipelines, multiple instructions per pipelines (notes only go over 1) going concurrently

Resolve hazards in pipelining thru forwarding. Need to understand dependencies between stages. Generally have data dependencies

(65): First exec we've loaded and accessed the register, then read it. Second, we have to read the value from register. Red line represents dependency.
Pipelining can forward the instruction ahead in time into the pipeline. We have a hazard control unit (that does something). In order to do this we have to figure out if instruction has dependency. Memory read/write phase is significant somehow. Pipeline has forwarding unit and hazarding unit. Execute instruction or write to memory depending on what these values are.
(69) Forwarding conditions.
Hardware dedicated to detecting hazards, etc Fwd A and Fwd B differ by

Structural, data, control hazards (don't worry about load hazard). Branches cause control hazards. Can deal with hazards through forwarding. Hazaards/stalls are bad, stalls reduce performance. Compiler wants to prevent hazards/stalls.

Branch hazards (78): Flush pipeline
Reducing branch delay: Jmps and branches are affected by branch target buffer
Branches can also be resolved using forwarding hardware. Branch prediction (85) Superscalar-> executing multiple instructions in groups of four

(88) BTB is a cache of addresses

On Exam: Branch prediction, dynamic branch prediction, hazards, little's law (study writeup, manipulate equation), iron law of computer performance (1.12 instructions, clocks per instructions, frequency), give example of multiple ISAs, describe basic components of computer, moore's law, how registers and memory work, multiplication/division hardware design (chapter2), RISC pipeline, bytes of instructions in RISC-V (32 bits: 4 bytes), 754 IEEE fp number formats for single and double digits, understand instruction formats, hw1 and 2