Info: Annotating ports with timing budgets for target frequency 48.00 MHz
Info:    remaining fanin includes F1 (net soc.psram_select)
Info:         driver = $auto$abc9.cc:774:abc9_module$1132646_SLICE.F1
Info:         user: $auto$abc9.cc:774:abc9_module$1132646_SLICE.C0
Info:         user: $auto$abc9.cc:774:abc9_module$1132646_SLICE.B1
Info:    remaining fanin includes F1 (net $abc$308925$techmap\soc.qpi_psram_I.$0\cf_wren[0:0])
Info:         driver = $abc$308925$soc.qpi_psram_I.cmd_fifo_I.lvl_dec$lut_SLICE.F1
Info:         user: $abc$308925$soc.qpi_psram_I.cmd_fifo_I.lvl_dec$lut_SLICE.DI1
Info:    remaining fanin includes F0 (net $abc$308925$techmap\soc.qpi_psram_I.$0\rf_overflow_clr[0:0])
Info:         driver = $abc$308925$techmap\soc.qpi_psram_I.$0\rf_overflow_clr[0:0]$lut_SLICE.F0
Info:         user: $abc$308925$techmap\soc.qpi_psram_I.$0\rf_overflow_clr[0:0]$lut_SLICE.DI0
Info:    remaining fanin includes F1 (net $abc$308925$techmap\soc.qpi_psram_I.$procmux$15449_Y)
Info:         driver = $abc$308925$soc.qpi_psram_I.we_csr$lut_SLICE.F1
Info:         user: $abc$308925$soc.qpi_psram_I.we_csr$lut_SLICE.DI1
Info:    remaining fanin includes F0 (net soc.qpi_psram_I.rd_rst)
Info:         driver = $auto$abc9.cc:774:abc9_module$1132646_SLICE.F0
Info:         user: $abc$308925$soc.qpi_psram_I.cmd_fifo_I.lvl_dec$lut_SLICE.B1
Info:         user: $abc$308925$techmap\soc.qpi_psram_I.$0\rf_overflow_clr[0:0]$lut_SLICE.B0
Info:         user: $abc$308925$soc.qpi_psram_I.we_csr$lut_SLICE.B1
Info:         user: $abc$308925$__17866__$lut_SLICE.LSR
Info:         user: $abc$308925$__18590__$lut_SLICE.LSR
Info:         user: $auto$abc9.cc:774:abc9_module$1132607_SLICE.LSR
Info:         user: $abc$308925$__19570__$lut_SLICE.LSR
Info:         user: $auto$abc9.cc:774:abc9_module$1132605_SLICE.LSR
Info:         user: $auto$abc9.cc:774:abc9_module$1132604_SLICE.LSR
Info:         user: $auto$abc9.cc:774:abc9_module$1132603_SLICE.LSR
Info:         user: $abc$308925$__21115__$lut_SLICE.LSR
Info:         user: $abc$308925$techmap\soc.qpi_psram_I.$ternary$qpi_cache/qpimem_iface_2x2w.v:268$1896_Y[8]$lut_SLICE.LSR
Info:         user: $abc$308925$__18389__$lut_SLICE.LSR
Info:         user: $abc$308925$techmap\soc.qpi_psram_I.$ternary$qpi_cache/qpimem_iface_2x2w.v:268$1896_Y[10]$lut_SLICE.LSR
Info:         user: $abc$308925$techmap\soc.qpi_psram_I.$ternary$qpi_cache/qpimem_iface_2x2w.v:268$1896_Y[11]$lut_SLICE.LSR
Info:         user: $abc$308925$__19693__$lut_SLICE.LSR
Info:         user: $abc$308925$__20168__$lut_SLICE.LSR
Info:         user: $abc$308925$techmap\soc.qpi_psram_I.$ternary$qpi_cache/qpimem_iface_2x2w.v:268$1896_Y[14]$lut_SLICE.LSR
Info:         user: $abc$308925$__20911__$lut_SLICE.LSR
Info:         user: $abc$308925$__18053__$lut_SLICE.LSR
Info:         user: $abc$308925$techmap\soc.qpi_psram_I.$ternary$qpi_cache/qpimem_iface_2x2w.v:268$1896_Y[17]$lut_SLICE.LSR
Info:         user: $abc$308925$__18992__$lut_SLICE.LSR
Info:         user: $abc$308925$__19247__$lut_SLICE.LSR
Info:         user: $abc$308925$__19886__$lut_SLICE.LSR
Info:         user: $abc$308925$__20081__$lut_SLICE.LSR
Info:         user: $abc$308925$__20473__$lut_SLICE.LSR
Info:         user: $abc$308925$__20861__$lut_SLICE.LSR
Info:         user: $abc$308925$__18257__$lut_SLICE.LSR
Info:         user: $abc$308925$techmap\soc.qpi_psram_I.$ternary$qpi_cache/qpimem_iface_2x2w.v:268$1896_Y[25]$lut_SLICE.LSR
Info:         user: $abc$308925$__18903__$lut_SLICE.LSR
Info:         user: $abc$308925$techmap\soc.qpi_psram_I.$ternary$qpi_cache/qpimem_iface_2x2w.v:268$1896_Y[27]$lut_SLICE.LSR
Info:         user: $abc$308925$techmap\soc.qpi_psram_I.$ternary$qpi_cache/qpimem_iface_2x2w.v:268$1896_Y[28]$lut_SLICE.LSR
Info:         user: $abc$308925$techmap\soc.qpi_psram_I.$ternary$qpi_cache/qpimem_iface_2x2w.v:268$1896_Y[29]$lut_SLICE.LSR
Info:         user: $abc$308925$techmap\soc.qpi_psram_I.$ternary$qpi_cache/qpimem_iface_2x2w.v:268$1896_Y[30]$lut_SLICE.LSR
Info:         user: $abc$308925$techmap\soc.qpi_psram_I.$ternary$qpi_cache/qpimem_iface_2x2w.v:268$1896_Y[31]$lut_SLICE.LSR
ERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc.