package body Utils is
      procedure Clock(signal C: out Bit; HT,LT: Time) is
      begin
	loop
		C <='1' after LT, '0' after LT + HT;
		wait for LT + HT;
	end loop;
      end;

    function Convert(N,L:Natural) return Bit_Vector is
	variable Temp: Bit_Vector(L - 1 downto 0);
	variable Value:Natural:= N;
    begin
		for i in Temp'Right to Temp'Left loop
			Temp(i):=Bit'Val(Value mod 2);
			Value:=Value / 2;
		end loop;
	return Temp;
   	end;

      function Convert(B:Bit_Vector) return Natural is
	variable Temp: Bit_Vector(B'Length-1 downto 0):=B;
	variable Value:Natural:= 0;
      begin
	for i in Temp'Right to Temp'Left loop
		if Temp(i) = '1' then
			Value:=Value + (2**i);
		 end if;
	end loop;
	return Value;
      end;

end Utils;

entity Multiplicador is

        port (
                CLK: in Bit;
                STB: in Bit;
                Z: in Bit_vector(3 downto 0);
                B: in Bit_vector(3 downto 0);
                DONE: out Bit;
                RESULT: out Bit_vector(7 downto 0));
        begin
        assert ((Z'Length <= 4)or(B'Length <= 4))
        report "La Entrada A o la B no debe ser mas ancha que 4"
        severity Failure;
end Multiplicador;

architecture coso of Multiplicador is


        component Latch8
                port(D: in Bit_Vector(7 downto 0); Clk: in Bit; Pre: in Bit; Clr: in Bit; Q:out Bit_Vector(7 downto 0));
        end component;
        component Controller
                port (STB, CLK, LSB, Stop: in Bit;
                Init, Shift, Add, Done: out Bit);
        end component;
        component Adder8
                port (A, B: in Bit_Vector(7 downto 0); Cin: in Bit; Cout: out Bit; Sum: out Bit_Vector(7 downto 0)); --S1 subtotal que entra al sumador
        end component;
        component ShiftN
                port (CLK: in Bit; CLR: in Bit; LD: in Bit;
                SH: in Bit; DIR: in Bit;
                D: in Bit_Vector; Q: out Bit_Vector);
        end component;

        signal CLR, LD, SH, DIR, INIT,ADD,INITneg: Bit:='0';
        signal D: Bit_Vector(1 to 4);
        signal Q: Bit_Vector(7 downto 0);
        signal QA: Bit_Vector(7 downto 0);
        signal K: bit_vector(7 downto 0);
        signal S1: bit_vector(7 downto 0);
        signal cout:bit;
        signal RES_SUMA: bit_vector(7 downto 0);
        signal Stop: bit;
        signal STB2: bit;
        signal Result2: bit_vector(7 downto 0);
        signal CLK2: bit;
        begin

                INITneg <=not INIT;
                Stop <= not (Q(7) or Q(6) or Q(5) or Q(4) or Q(3) or Q(2) or Q(1) or Q(0));
                SRAA: ShiftN port map (CLK,'0',INIT,SH,'0',Z,Q);
                SRB: ShiftN port map (CLK, '0',INIT,SH,'1',B,QA);
                CONTROLADOR: Controller port map(STB,CLK,Q(0),Stop,INIT,SH,ADD,DONE);
                ACUMULADOR1: Latch8 port map (RES_SUMA,ADD,'1',INITneg,S1);
                SUMADOR: Adder8 port map(S1,QA,'0',cout,RES_SUMA);
                ACUMULADOR2: Latch8 port map (S1,CLK,'1',INITneg,Result2);
				RESULT<=Result2 when Stop = '1';

        end;

-----Testbench------

entity Test_Mult is end;
use work.Utils.all;
        architecture tuvieja of Test_Mult is
        component Multiplicador port (CLK: in bit; STB: in bit; Z: in bit_vector(3 downto 0); b: in bit_vector(3 downto 0); DONE: out bit; RESULT: out bit_vector (7 downto 0));
                end component;
                signal A, B: Bit_Vector(3 downto 0);
        signal Clk, STB, Done: bit;
                signal resultau: bit_vector (7 downto 0);

begin
        Mul: Multiplicador port map (Clk,STB,A,B,Done,resultau);
        --Clock:  Clk <= not Clk after 20 ns;
        Clock:  CLK <= not (CLK) after 10 ns;
        Roto: process

        --variable op1,op2: bit_vector(3 downto 0);

        begin

        --STB <= '1', '0' after 400000 ns;

		--A<="0110" ;

		--B<="1110" ;
		--wait for 240 ns;


		--A<="1000";

		--B<="0001";
		--wait for 240 ns;

		--A<="0101";

		--B<="1010";wait for 10 ns;

		for i in 0 to 15 loop

			A<=Convert (i, A'Length) after 10 ns;

			--wait for 10 ns;
			for j in 0 to 15 loop
				B<=Convert (j, B'Length); --after 200ns;

 			-- sacar promedio := tiempoTotal/15*15

			end loop;
			--wait until (DONE='1');
			    end loop;

         wait;

        end process;


end;


entity Test_Mult2 is end;
USE std.textio.all;
use work.Utils.all;

architecture nisman of Test_Mult2 is

		component Multiplicador port (CLK: in bit; STB: in bit; Z: in bit_vector(3 downto 0); b: in bit_vector(3 downto 0); DONE: out bit; RESULT: out bit_vector (7 downto 0));
			end component;

		signal A, B: Bit_Vector(3 downto 0);
        signal Clk, STB, Done: bit;
		signal resultau: bit_vector (7 downto 0);
		CONSTANT mensaje1: String:="Ingrese el primer numero";
		CONSTANT mensaje2: String:="Ingrese el segundo numero";
		CONSTANT mensaje3: String:="Quiere realizar otra operacion, '1' si, '0' no ?";

begin
		Mul: Multiplicador port map (Clk,STB,A,B,Done,resultau);

	Clock:  CLK <= not (CLK) after 10 ns;




	pro:process

	variable linea1: line;
	variable linea2:line;
	variable linea3:line;
	variable lineaA:line;
	variable lineaB:line;
	variable lineaD:line;
	variable numA: integer;
	variable numB: integer;

	variable decision:integer;
	variable droopy: side;

	begin
		write (linea1,mensaje1,droopy,mensaje1'length);
		write (linea2,mensaje2,droopy,mensaje2'length);
		write (linea3,mensaje3,droopy,mensaje3'length);
		decision:=1;
		wait for 30ns;
		while (decision=1) loop

			writeline(output,linea1);
			readline(input,lineaA);
			read(lineaA,numA);
			A<=Convert (numA, A'Length);
			writeline(output,linea2);
			readline(input,lineaB);
			read(lineaB,numB);
			B<=Convert (numB, B'Length);
			STB<='1', '0' after 30ns;
			wait until (DONE='1');
			writeline(output,linea3);
			readline(input,lineaD);
			read(lineaD, decision);
			--agregar write para imprimer enconsola de resultau
		end loop;
		wait;

	end process;

end;