module mojo_top(
    // 50MHz clock input
    input clk,
    // Input from reset button (active low)
    input rst_n,
    // cclk input from AVR, high when AVR is ready
    input cclk,
    // Outputs to the 8 onboard LEDs
    output[7:0]led,
    // AVR SPI connections
    output spi_miso,
    input spi_ss,
    input spi_mosi,
    input spi_sck,
    // AVR ADC channel select
    output [3:0] spi_channel,
    // Serial connections
    input avr_tx, // AVR Tx => FPGA Rx
    output avr_rx, // AVR Rx => FPGA Tx
    input avr_rx_busy, // AVR Rx buffer full

     output reg[2:0] levels,
     output reg[8:0] columns
    );

wire rst = ~rst_n; // make reset active high

// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;

assign led = 8'b0;


/* clk divider to reduce the LED blink speed to 1/10 of a second
*/
reg[22:0] div;
wire cube_clk = (div == 23'h4c4b40);
always @ (posedge clk) begin
    if(cube_clk)
        div <= 23'b0;
    else
        div <= div + 1;
end

wire [1:0] lvl; //level vector for the LED_counter driver
wire [3:0] clm; //column vector for the LED_counter driver
LED_counter cube(.clk(cube_clk), .level(lvl), .column(clm));

/* Depending on the count, turns on one of the levels.
*/
always @ (lvl) begin
    case(lvl)
        0: levels <= 3'b001;
        1: levels <= 3'b010;
        2: levels <= 3'b100;
        default: levels <= 3'b000;
    endcase
end


/* Depending on the count, turns on one of the columns.
*/
always @ (clm) begin
    case(clm)
        0: columns <= 9'd1;
        1: columns <= 9'd2;
        2: columns <= 9'd4;
        3: columns <= 9'd8;
        4: columns <= 9'd16;
        5: columns <= 9'd32;
        6: columns <= 9'd64;
        7: columns <= 9'd128;
        8: columns <= 9'd256;
        default: columns <= 9'd0;
    endcase
end

endmodule