clk_a : in std_logic;
clk_b : in std_logic;
reset : in std_logic;

-- cross-domain counter
signal frm_cnt : standard_logic_vector(7 downto 0);
-- control signal: increment counter (synced to clk_a)
signal frm_cnt_inc : std_logic;
-- control signal: decrement counter (synced to clk_b)
signal frm_cnt_dec : std_logic;
-- control signal, perform action on the counter
signal frm_cnt_modif : std_logic;

frm_cnt_modif <= frm_cnt_inc or frm_cnt_dec; -- can also be xored

frame_counter : process(frm_cnt_modif, reset)
begin
  if reset = RST_ACTIVE then
    frm_cnt <= (others => '0');
  elsif rising_edge(frm_cnt_modif) then
    if frm_cnt_inc = '1' then
      frm_cnt <= incr_vec(frm_cnt);
    elsif frm_cnt_dec = '1' then
      frm_cnt <= decr_vec(frm_cnt);
    end if;
  end if;
end process;

control_synchronizer : process(clk_b, reset)
begin
  if reset = RST_ACTIVE then
    frm_cnt_inc_sync <= '0';
  elsif rising_edge(clk_b) then
    if frm_cnt_inc_sync = '1' then
      frm_cnt_inc_sync <= '0';
    elsif frm_cnt_inc = '1' then
      frm_cnt_inc_sync <= '1';
    else
      frm_cnt_inc_sync <= '0';
    end if;
  end if;
end process;