bmx34

Untitled

Nov 10th, 2020
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  1. /dts-v1/;
  2.  
  3. / {
  4. interrupt-parent = <0x01>;
  5. #address-cells = <0x01>;
  6. #size-cells = <0x01>;
  7. model = "Xunlong Orange Pi PC Plus";
  8. compatible = "xunlong,orangepi-pc-plus\0allwinner,sun8i-h3";
  9.  
  10. chosen {
  11. #address-cells = <0x01>;
  12. #size-cells = <0x01>;
  13. ranges;
  14. stdout-path = "serial0:115200n8";
  15.  
  16. framebuffer-hdmi {
  17. compatible = "allwinner,simple-framebuffer\0simple-framebuffer";
  18. allwinner,pipeline = "mixer0-lcd0-hdmi";
  19. clocks = <0x02 0x06 0x03 0x66 0x03 0x6f>;
  20. status = "disabled";
  21. };
  22.  
  23. framebuffer-tve {
  24. compatible = "allwinner,simple-framebuffer\0simple-framebuffer";
  25. allwinner,pipeline = "mixer1-lcd1-tve";
  26. clocks = <0x02 0x07 0x03 0x67>;
  27. status = "disabled";
  28. };
  29. };
  30.  
  31. sound {
  32. compatible = "simple-audio-card";
  33. simple-audio-card,format = "i2s";
  34. simple-audio-card,name = "allwinner-hdmi";
  35. simple-audio-card,mclk-fs = <0x80>;
  36. simple-audio-card,frame-inversion;
  37.  
  38. simple-audio-card,codec {
  39. sound-dai = <0x04>;
  40. };
  41.  
  42. simple-audio-card,cpu {
  43. sound-dai = <0x05>;
  44. dai-tdm-slot-num = <0x02>;
  45. dai-tdm-slot-width = <0x20>;
  46. };
  47. };
  48.  
  49. clocks {
  50. #address-cells = <0x01>;
  51. #size-cells = <0x01>;
  52. ranges;
  53.  
  54. osc24M_clk {
  55. #clock-cells = <0x00>;
  56. compatible = "fixed-clock";
  57. clock-frequency = <0x16e3600>;
  58. clock-accuracy = <0xc350>;
  59. clock-output-names = "osc24M";
  60. phandle = <0x11>;
  61. };
  62.  
  63. osc32k_clk {
  64. #clock-cells = <0x00>;
  65. compatible = "fixed-clock";
  66. clock-frequency = <0x8000>;
  67. clock-accuracy = <0xc350>;
  68. clock-output-names = "ext_osc32k";
  69. phandle = <0x25>;
  70. };
  71. };
  72.  
  73. display-engine {
  74. compatible = "allwinner,sun8i-h3-display-engine";
  75. allwinner,pipelines = <0x06>;
  76. status = "okay";
  77. };
  78.  
  79. soc {
  80. compatible = "simple-bus";
  81. #address-cells = <0x01>;
  82. #size-cells = <0x01>;
  83. dma-ranges;
  84. ranges;
  85.  
  86. clock@1000000 {
  87. reg = <0x1000000 0x10000>;
  88. clocks = <0x03 0x30 0x03 0x65>;
  89. clock-names = "bus\0mod";
  90. resets = <0x03 0x22>;
  91. #clock-cells = <0x01>;
  92. #reset-cells = <0x01>;
  93. compatible = "allwinner,sun8i-h3-de2-clk";
  94. phandle = <0x02>;
  95. };
  96.  
  97. mixer@1100000 {
  98. compatible = "allwinner,sun8i-h3-de2-mixer-0";
  99. reg = <0x1100000 0x100000>;
  100. clocks = <0x02 0x00 0x02 0x06>;
  101. clock-names = "bus\0mod";
  102. resets = <0x02 0x00>;
  103. phandle = <0x06>;
  104.  
  105. ports {
  106. #address-cells = <0x01>;
  107. #size-cells = <0x00>;
  108.  
  109. port@1 {
  110. reg = <0x01>;
  111.  
  112. endpoint {
  113. remote-endpoint = <0x07>;
  114. phandle = <0x08>;
  115. };
  116. };
  117. };
  118. };
  119.  
  120. dma-controller@1c02000 {
  121. compatible = "allwinner,sun8i-h3-dma";
  122. reg = <0x1c02000 0x1000>;
  123. interrupts = <0x00 0x32 0x04>;
  124. clocks = <0x03 0x15>;
  125. resets = <0x03 0x06>;
  126. #dma-cells = <0x01>;
  127. phandle = <0x16>;
  128. };
  129.  
  130. lcd-controller@1c0c000 {
  131. compatible = "allwinner,sun8i-h3-tcon-tv\0allwinner,sun8i-a83t-tcon-tv";
  132. reg = <0x1c0c000 0x1000>;
  133. interrupts = <0x00 0x56 0x04>;
  134. clocks = <0x03 0x2a 0x03 0x66>;
  135. clock-names = "ahb\0tcon-ch1";
  136. resets = <0x03 0x1b>;
  137. reset-names = "lcd";
  138.  
  139. ports {
  140. #address-cells = <0x01>;
  141. #size-cells = <0x00>;
  142.  
  143. port@0 {
  144. reg = <0x00>;
  145.  
  146. endpoint {
  147. remote-endpoint = <0x08>;
  148. phandle = <0x07>;
  149. };
  150. };
  151.  
  152. port@1 {
  153. #address-cells = <0x01>;
  154. #size-cells = <0x00>;
  155. reg = <0x01>;
  156.  
  157. endpoint@1 {
  158. reg = <0x01>;
  159. remote-endpoint = <0x09>;
  160. phandle = <0x23>;
  161. };
  162. };
  163. };
  164. };
  165.  
  166. mmc@1c0f000 {
  167. reg = <0x1c0f000 0x1000>;
  168. pinctrl-names = "default";
  169. pinctrl-0 = <0x0a>;
  170. resets = <0x03 0x07>;
  171. reset-names = "ahb";
  172. interrupts = <0x00 0x3c 0x04>;
  173. status = "okay";
  174. #address-cells = <0x01>;
  175. #size-cells = <0x00>;
  176. compatible = "allwinner,sun7i-a20-mmc";
  177. clocks = <0x03 0x16 0x03 0x47 0x03 0x49 0x03 0x48>;
  178. clock-names = "ahb\0mmc\0output\0sample";
  179. vmmc-supply = <0x0b>;
  180. bus-width = <0x04>;
  181. cd-gpios = <0x0c 0x05 0x06 0x01>;
  182. };
  183.  
  184. mmc@1c10000 {
  185. reg = <0x1c10000 0x1000>;
  186. pinctrl-names = "default";
  187. pinctrl-0 = <0x0d>;
  188. resets = <0x03 0x08>;
  189. reset-names = "ahb";
  190. interrupts = <0x00 0x3d 0x04>;
  191. status = "okay";
  192. #address-cells = <0x01>;
  193. #size-cells = <0x00>;
  194. compatible = "allwinner,sun7i-a20-mmc";
  195. clocks = <0x03 0x17 0x03 0x4a 0x03 0x4c 0x03 0x4b>;
  196. clock-names = "ahb\0mmc\0output\0sample";
  197. vmmc-supply = <0x0b>;
  198. bus-width = <0x04>;
  199. non-removable;
  200.  
  201. sdio_wifi@1 {
  202. reg = <0x01>;
  203. };
  204. };
  205.  
  206. mmc@1c11000 {
  207. reg = <0x1c11000 0x1000>;
  208. resets = <0x03 0x09>;
  209. reset-names = "ahb";
  210. interrupts = <0x00 0x3e 0x04>;
  211. status = "okay";
  212. #address-cells = <0x01>;
  213. #size-cells = <0x00>;
  214. compatible = "allwinner,sun7i-a20-mmc";
  215. clocks = <0x03 0x18 0x03 0x4d 0x03 0x4f 0x03 0x4e>;
  216. clock-names = "ahb\0mmc\0output\0sample";
  217. pinctrl-names = "default";
  218. pinctrl-0 = <0x0e>;
  219. vmmc-supply = <0x0b>;
  220. bus-width = <0x08>;
  221. non-removable;
  222. cap-mmc-hw-reset;
  223. };
  224.  
  225. eeprom@1c14000 {
  226. reg = <0x1c14000 0x400>;
  227. #address-cells = <0x01>;
  228. #size-cells = <0x01>;
  229. compatible = "allwinner,sun8i-h3-sid";
  230.  
  231. thermal-sensor-calibration@34 {
  232. reg = <0x34 0x04>;
  233. phandle = <0x2d>;
  234. };
  235. };
  236.  
  237. mailbox@1c17000 {
  238. compatible = "allwinner,sun8i-h3-msgbox\0allwinner,sun6i-a31-msgbox";
  239. reg = <0x1c17000 0x1000>;
  240. clocks = <0x03 0x32>;
  241. resets = <0x03 0x24>;
  242. interrupts = <0x00 0x31 0x04>;
  243. #mbox-cells = <0x01>;
  244. };
  245.  
  246. usb@1c19000 {
  247. compatible = "allwinner,sun8i-h3-musb";
  248. reg = <0x1c19000 0x400>;
  249. clocks = <0x03 0x20>;
  250. resets = <0x03 0x11>;
  251. interrupts = <0x00 0x47 0x04>;
  252. interrupt-names = "mc";
  253. phys = <0x0f 0x00>;
  254. phy-names = "usb";
  255. extcon = <0x0f 0x00>;
  256. dr_mode = "otg";
  257. status = "okay";
  258. };
  259.  
  260. phy@1c19400 {
  261. compatible = "allwinner,sun8i-h3-usb-phy";
  262. reg = <0x1c19400 0x2c 0x1c1a800 0x04 0x1c1b800 0x04 0x1c1c800 0x04 0x1c1d800 0x04>;
  263. reg-names = "phy_ctrl\0pmu0\0pmu1\0pmu2\0pmu3";
  264. clocks = <0x03 0x58 0x03 0x59 0x03 0x5a 0x03 0x5b>;
  265. clock-names = "usb0_phy\0usb1_phy\0usb2_phy\0usb3_phy";
  266. resets = <0x03 0x00 0x03 0x01 0x03 0x02 0x03 0x03>;
  267. reset-names = "usb0_reset\0usb1_reset\0usb2_reset\0usb3_reset";
  268. status = "okay";
  269. #phy-cells = <0x01>;
  270. usb0_id_det-gpios = <0x0c 0x06 0x0c 0x00>;
  271. usb0_vbus-supply = <0x10>;
  272. phandle = <0x0f>;
  273. };
  274.  
  275. usb@1c1a000 {
  276. compatible = "allwinner,sun8i-h3-ehci\0generic-ehci";
  277. reg = <0x1c1a000 0x100>;
  278. interrupts = <0x00 0x48 0x04>;
  279. clocks = <0x03 0x21 0x03 0x25>;
  280. resets = <0x03 0x12 0x03 0x16>;
  281. status = "okay";
  282. };
  283.  
  284. usb@1c1a400 {
  285. compatible = "allwinner,sun8i-h3-ohci\0generic-ohci";
  286. reg = <0x1c1a400 0x100>;
  287. interrupts = <0x00 0x49 0x04>;
  288. clocks = <0x03 0x21 0x03 0x25 0x03 0x5c>;
  289. resets = <0x03 0x12 0x03 0x16>;
  290. status = "okay";
  291. };
  292.  
  293. usb@1c1b000 {
  294. compatible = "allwinner,sun8i-h3-ehci\0generic-ehci";
  295. reg = <0x1c1b000 0x100>;
  296. interrupts = <0x00 0x4a 0x04>;
  297. clocks = <0x03 0x22 0x03 0x26>;
  298. resets = <0x03 0x13 0x03 0x17>;
  299. phys = <0x0f 0x01>;
  300. phy-names = "usb";
  301. status = "okay";
  302. };
  303.  
  304. usb@1c1b400 {
  305. compatible = "allwinner,sun8i-h3-ohci\0generic-ohci";
  306. reg = <0x1c1b400 0x100>;
  307. interrupts = <0x00 0x4b 0x04>;
  308. clocks = <0x03 0x22 0x03 0x26 0x03 0x5d>;
  309. resets = <0x03 0x13 0x03 0x17>;
  310. phys = <0x0f 0x01>;
  311. phy-names = "usb";
  312. status = "okay";
  313. };
  314.  
  315. usb@1c1c000 {
  316. compatible = "allwinner,sun8i-h3-ehci\0generic-ehci";
  317. reg = <0x1c1c000 0x100>;
  318. interrupts = <0x00 0x4c 0x04>;
  319. clocks = <0x03 0x23 0x03 0x27>;
  320. resets = <0x03 0x14 0x03 0x18>;
  321. phys = <0x0f 0x02>;
  322. phy-names = "usb";
  323. status = "okay";
  324. };
  325.  
  326. usb@1c1c400 {
  327. compatible = "allwinner,sun8i-h3-ohci\0generic-ohci";
  328. reg = <0x1c1c400 0x100>;
  329. interrupts = <0x00 0x4d 0x04>;
  330. clocks = <0x03 0x23 0x03 0x27 0x03 0x5e>;
  331. resets = <0x03 0x14 0x03 0x18>;
  332. phys = <0x0f 0x02>;
  333. phy-names = "usb";
  334. status = "okay";
  335. };
  336.  
  337. usb@1c1d000 {
  338. compatible = "allwinner,sun8i-h3-ehci\0generic-ehci";
  339. reg = <0x1c1d000 0x100>;
  340. interrupts = <0x00 0x4e 0x04>;
  341. clocks = <0x03 0x24 0x03 0x28>;
  342. resets = <0x03 0x15 0x03 0x19>;
  343. phys = <0x0f 0x03>;
  344. phy-names = "usb";
  345. status = "okay";
  346. };
  347.  
  348. usb@1c1d400 {
  349. compatible = "allwinner,sun8i-h3-ohci\0generic-ohci";
  350. reg = <0x1c1d400 0x100>;
  351. interrupts = <0x00 0x4f 0x04>;
  352. clocks = <0x03 0x24 0x03 0x28 0x03 0x5f>;
  353. resets = <0x03 0x15 0x03 0x19>;
  354. phys = <0x0f 0x03>;
  355. phy-names = "usb";
  356. status = "okay";
  357. };
  358.  
  359. clock@1c20000 {
  360. reg = <0x1c20000 0x400>;
  361. clocks = <0x11 0x12 0x00>;
  362. clock-names = "hosc\0losc";
  363. #clock-cells = <0x01>;
  364. #reset-cells = <0x01>;
  365. compatible = "allwinner,sun8i-h3-ccu";
  366. phandle = <0x03>;
  367. };
  368.  
  369. pinctrl@1c20800 {
  370. reg = <0x1c20800 0x400>;
  371. interrupts = <0x00 0x0b 0x04 0x00 0x11 0x04>;
  372. clocks = <0x03 0x36 0x11 0x12 0x00>;
  373. clock-names = "apb\0hosc\0losc";
  374. gpio-controller;
  375. #gpio-cells = <0x03>;
  376. interrupt-controller;
  377. #interrupt-cells = <0x03>;
  378. compatible = "allwinner,sun8i-h3-pinctrl";
  379. phandle = <0x0c>;
  380.  
  381. csi-pins {
  382. pins = "PE0\0PE2\0PE3\0PE4\0PE5\0PE6\0PE7\0PE8\0PE9\0PE10\0PE11";
  383. function = "csi";
  384. phandle = <0x21>;
  385. };
  386.  
  387. emac-rgmii-pins {
  388. pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD7\0PD8\0PD9\0PD10\0PD12\0PD13\0PD15\0PD16\0PD17";
  389. function = "emac";
  390. drive-strength = <0x28>;
  391. };
  392.  
  393. i2c0-pins {
  394. pins = "PA11\0PA12";
  395. function = "i2c0";
  396. phandle = <0x1e>;
  397. };
  398.  
  399. i2c1-pins {
  400. pins = "PA18\0PA19";
  401. function = "i2c1";
  402. phandle = <0x1f>;
  403. };
  404.  
  405. i2c2-pins {
  406. pins = "PE12\0PE13";
  407. function = "i2c2";
  408. phandle = <0x20>;
  409. };
  410.  
  411. mmc0-pins {
  412. pins = "PF0\0PF1\0PF2\0PF3\0PF4\0PF5";
  413. function = "mmc0";
  414. drive-strength = <0x1e>;
  415. bias-pull-up;
  416. phandle = <0x0a>;
  417. };
  418.  
  419. mmc1-pins {
  420. pins = "PG0\0PG1\0PG2\0PG3\0PG4\0PG5";
  421. function = "mmc1";
  422. drive-strength = <0x1e>;
  423. bias-pull-up;
  424. phandle = <0x0d>;
  425. };
  426.  
  427. mmc2-8bit-pins {
  428. pins = "PC5\0PC6\0PC8\0PC9\0PC10\0PC11\0PC12\0PC13\0PC14\0PC15\0PC16";
  429. function = "mmc2";
  430. drive-strength = <0x28>;
  431. bias-pull-up;
  432. phandle = <0x0e>;
  433. };
  434.  
  435. spdif-tx-pin {
  436. pins = "PA17";
  437. function = "spdif";
  438. };
  439.  
  440. spi0-pins {
  441. pins = "PC0\0PC1\0PC2\0PC3";
  442. function = "spi0";
  443. phandle = <0x17>;
  444. };
  445.  
  446. spi1-pins {
  447. pins = "PA15\0PA16\0PA14\0PA13";
  448. function = "spi1";
  449. phandle = <0x18>;
  450. };
  451.  
  452. uart0-pa-pins {
  453. pins = "PA4\0PA5";
  454. function = "uart0";
  455. phandle = <0x1a>;
  456. };
  457.  
  458. uart1-pins {
  459. pins = "PG6\0PG7";
  460. function = "uart1";
  461. phandle = <0x1b>;
  462. };
  463.  
  464. uart1-rts-cts-pins {
  465. pins = "PG8\0PG9";
  466. function = "uart1";
  467. };
  468.  
  469. uart2-pins {
  470. pins = "PA0\0PA1";
  471. function = "uart2";
  472. phandle = <0x1c>;
  473. };
  474.  
  475. uart2-rts-cts-pins {
  476. pins = "PA2\0PA3";
  477. function = "uart2";
  478. };
  479.  
  480. uart3-pins {
  481. pins = "PA13\0PA14";
  482. function = "uart3";
  483. phandle = <0x1d>;
  484. };
  485.  
  486. uart3-rts-cts-pins {
  487. pins = "PA15\0PA16";
  488. function = "uart3";
  489. };
  490. };
  491.  
  492. timer@1c20c00 {
  493. compatible = "allwinner,sun8i-a23-timer";
  494. reg = <0x1c20c00 0xa0>;
  495. interrupts = <0x00 0x12 0x04 0x00 0x13 0x04>;
  496. clocks = <0x11>;
  497. };
  498.  
  499. ethernet@1c30000 {
  500. compatible = "allwinner,sun8i-h3-emac";
  501. syscon = <0x13>;
  502. reg = <0x1c30000 0x10000>;
  503. interrupts = <0x00 0x52 0x04>;
  504. interrupt-names = "macirq";
  505. resets = <0x03 0x0c>;
  506. reset-names = "stmmaceth";
  507. clocks = <0x03 0x1b>;
  508. clock-names = "stmmaceth";
  509. status = "okay";
  510. phy-handle = <0x14>;
  511. phy-mode = "mii";
  512. allwinner,leds-active-low;
  513.  
  514. mdio {
  515. #address-cells = <0x01>;
  516. #size-cells = <0x00>;
  517. compatible = "snps,dwmac-mdio";
  518. phandle = <0x15>;
  519. };
  520.  
  521. mdio-mux {
  522. compatible = "allwinner,sun8i-h3-mdio-mux";
  523. #address-cells = <0x01>;
  524. #size-cells = <0x00>;
  525. mdio-parent-bus = <0x15>;
  526.  
  527. mdio@1 {
  528. compatible = "allwinner,sun8i-h3-mdio-internal";
  529. reg = <0x01>;
  530. #address-cells = <0x01>;
  531. #size-cells = <0x00>;
  532.  
  533. ethernet-phy@1 {
  534. compatible = "ethernet-phy-ieee802.3-c22";
  535. reg = <0x01>;
  536. clocks = <0x03 0x43>;
  537. resets = <0x03 0x27>;
  538. phandle = <0x14>;
  539. };
  540. };
  541.  
  542. mdio@2 {
  543. reg = <0x02>;
  544. #address-cells = <0x01>;
  545. #size-cells = <0x00>;
  546. };
  547. };
  548. };
  549.  
  550. dram-controller@1c62000 {
  551. compatible = "allwinner,sun8i-h3-mbus";
  552. reg = <0x1c62000 0x1000>;
  553. clocks = <0x03 0x71>;
  554. #address-cells = <0x01>;
  555. #size-cells = <0x01>;
  556. dma-ranges = <0x00 0x40000000 0xc0000000>;
  557. #interconnect-cells = <0x01>;
  558. phandle = <0x2a>;
  559. };
  560.  
  561. spi@1c68000 {
  562. compatible = "allwinner,sun8i-h3-spi";
  563. reg = <0x1c68000 0x1000>;
  564. interrupts = <0x00 0x41 0x04>;
  565. clocks = <0x03 0x1e 0x03 0x52>;
  566. clock-names = "ahb\0mod";
  567. dmas = <0x16 0x17 0x16 0x17>;
  568. dma-names = "rx\0tx";
  569. pinctrl-names = "default";
  570. pinctrl-0 = <0x17>;
  571. resets = <0x03 0x0f>;
  572. status = "disabled";
  573. #address-cells = <0x01>;
  574. #size-cells = <0x00>;
  575. };
  576.  
  577. spi@1c69000 {
  578. compatible = "allwinner,sun8i-h3-spi";
  579. reg = <0x1c69000 0x1000>;
  580. interrupts = <0x00 0x42 0x04>;
  581. clocks = <0x03 0x1f 0x03 0x53>;
  582. clock-names = "ahb\0mod";
  583. dmas = <0x16 0x18 0x16 0x18>;
  584. dma-names = "rx\0tx";
  585. pinctrl-names = "default";
  586. pinctrl-0 = <0x18>;
  587. resets = <0x03 0x10>;
  588. status = "disabled";
  589. #address-cells = <0x01>;
  590. #size-cells = <0x00>;
  591. };
  592.  
  593. watchdog@1c20ca0 {
  594. compatible = "allwinner,sun6i-a31-wdt";
  595. reg = <0x1c20ca0 0x20>;
  596. interrupts = <0x00 0x19 0x04>;
  597. clocks = <0x11>;
  598. };
  599.  
  600. spdif@1c21000 {
  601. #sound-dai-cells = <0x00>;
  602. compatible = "allwinner,sun8i-h3-spdif";
  603. reg = <0x1c21000 0x400>;
  604. interrupts = <0x00 0x0c 0x04>;
  605. clocks = <0x03 0x35 0x03 0x57>;
  606. resets = <0x03 0x29>;
  607. clock-names = "apb\0spdif";
  608. dmas = <0x16 0x02>;
  609. dma-names = "tx";
  610. status = "okay";
  611. };
  612.  
  613. pwm@1c21400 {
  614. compatible = "allwinner,sun8i-h3-pwm";
  615. reg = <0x1c21400 0x08>;
  616. clocks = <0x11>;
  617. #pwm-cells = <0x03>;
  618. status = "disabled";
  619. };
  620.  
  621. i2s@1c22000 {
  622. #sound-dai-cells = <0x00>;
  623. compatible = "allwinner,sun8i-h3-i2s";
  624. reg = <0x1c22000 0x400>;
  625. interrupts = <0x00 0x0d 0x04>;
  626. clocks = <0x03 0x38 0x03 0x54>;
  627. clock-names = "apb\0mod";
  628. dmas = <0x16 0x03 0x16 0x03>;
  629. resets = <0x03 0x2b>;
  630. dma-names = "rx\0tx";
  631. status = "disabled";
  632. };
  633.  
  634. i2s@1c22400 {
  635. #sound-dai-cells = <0x00>;
  636. compatible = "allwinner,sun8i-h3-i2s";
  637. reg = <0x1c22400 0x400>;
  638. interrupts = <0x00 0x0e 0x04>;
  639. clocks = <0x03 0x39 0x03 0x55>;
  640. clock-names = "apb\0mod";
  641. dmas = <0x16 0x04 0x16 0x04>;
  642. resets = <0x03 0x2c>;
  643. dma-names = "rx\0tx";
  644. status = "disabled";
  645. };
  646.  
  647. i2s@1c22800 {
  648. #sound-dai-cells = <0x00>;
  649. compatible = "allwinner,sun8i-h3-i2s";
  650. reg = <0x1c22800 0x400>;
  651. interrupts = <0x00 0x0f 0x04>;
  652. clocks = <0x03 0x3a 0x03 0x56>;
  653. clock-names = "apb\0mod";
  654. dmas = <0x16 0x1b>;
  655. resets = <0x03 0x2d>;
  656. dma-names = "tx";
  657. allwinner,playback-channels = <0x08>;
  658. phandle = <0x05>;
  659. };
  660.  
  661. codec@1c22c00 {
  662. #sound-dai-cells = <0x00>;
  663. compatible = "allwinner,sun8i-h3-codec";
  664. reg = <0x1c22c00 0x400>;
  665. interrupts = <0x00 0x1d 0x04>;
  666. clocks = <0x03 0x34 0x03 0x6d>;
  667. clock-names = "apb\0codec";
  668. resets = <0x03 0x28>;
  669. dmas = <0x16 0x0f 0x16 0x0f>;
  670. dma-names = "rx\0tx";
  671. allwinner,codec-analog-controls = <0x19>;
  672. status = "okay";
  673. allwinner,audio-routing = "Line Out\0LINEOUT\0MIC1\0Mic\0Mic\0MBIAS";
  674. };
  675.  
  676. serial@1c28000 {
  677. compatible = "snps,dw-apb-uart";
  678. reg = <0x1c28000 0x400>;
  679. interrupts = <0x00 0x00 0x04>;
  680. reg-shift = <0x02>;
  681. reg-io-width = <0x04>;
  682. clocks = <0x03 0x3e>;
  683. resets = <0x03 0x31>;
  684. dmas = <0x16 0x06 0x16 0x06>;
  685. dma-names = "rx\0tx";
  686. status = "okay";
  687. pinctrl-names = "default";
  688. pinctrl-0 = <0x1a>;
  689. };
  690.  
  691. serial@1c28400 {
  692. compatible = "snps,dw-apb-uart";
  693. reg = <0x1c28400 0x400>;
  694. interrupts = <0x00 0x01 0x04>;
  695. reg-shift = <0x02>;
  696. reg-io-width = <0x04>;
  697. clocks = <0x03 0x3f>;
  698. resets = <0x03 0x32>;
  699. dmas = <0x16 0x07 0x16 0x07>;
  700. dma-names = "rx\0tx";
  701. status = "disabled";
  702. pinctrl-names = "default";
  703. pinctrl-0 = <0x1b>;
  704. };
  705.  
  706. serial@1c28800 {
  707. compatible = "snps,dw-apb-uart";
  708. reg = <0x1c28800 0x400>;
  709. interrupts = <0x00 0x02 0x04>;
  710. reg-shift = <0x02>;
  711. reg-io-width = <0x04>;
  712. clocks = <0x03 0x40>;
  713. resets = <0x03 0x33>;
  714. dmas = <0x16 0x08 0x16 0x08>;
  715. dma-names = "rx\0tx";
  716. status = "disabled";
  717. pinctrl-names = "default";
  718. pinctrl-0 = <0x1c>;
  719. };
  720.  
  721. serial@1c28c00 {
  722. compatible = "snps,dw-apb-uart";
  723. reg = <0x1c28c00 0x400>;
  724. interrupts = <0x00 0x03 0x04>;
  725. reg-shift = <0x02>;
  726. reg-io-width = <0x04>;
  727. clocks = <0x03 0x41>;
  728. resets = <0x03 0x34>;
  729. dmas = <0x16 0x09 0x16 0x09>;
  730. dma-names = "rx\0tx";
  731. status = "disabled";
  732. pinctrl-names = "default";
  733. pinctrl-0 = <0x1d>;
  734. };
  735.  
  736. i2c@1c2ac00 {
  737. compatible = "allwinner,sun6i-a31-i2c";
  738. reg = <0x1c2ac00 0x400>;
  739. interrupts = <0x00 0x06 0x04>;
  740. clocks = <0x03 0x3b>;
  741. resets = <0x03 0x2e>;
  742. pinctrl-names = "default";
  743. pinctrl-0 = <0x1e>;
  744. status = "disabled";
  745. #address-cells = <0x01>;
  746. #size-cells = <0x00>;
  747. };
  748.  
  749. i2c@1c2b000 {
  750. compatible = "allwinner,sun6i-a31-i2c";
  751. reg = <0x1c2b000 0x400>;
  752. interrupts = <0x00 0x07 0x04>;
  753. clocks = <0x03 0x3c>;
  754. resets = <0x03 0x2f>;
  755. pinctrl-names = "default";
  756. pinctrl-0 = <0x1f>;
  757. status = "disabled";
  758. #address-cells = <0x01>;
  759. #size-cells = <0x00>;
  760. };
  761.  
  762. i2c@1c2b400 {
  763. compatible = "allwinner,sun6i-a31-i2c";
  764. reg = <0x1c2b400 0x400>;
  765. interrupts = <0x00 0x08 0x04>;
  766. clocks = <0x03 0x3d>;
  767. resets = <0x03 0x30>;
  768. pinctrl-names = "default";
  769. pinctrl-0 = <0x20>;
  770. status = "disabled";
  771. #address-cells = <0x01>;
  772. #size-cells = <0x00>;
  773. };
  774.  
  775. interrupt-controller@1c81000 {
  776. compatible = "arm,gic-400";
  777. reg = <0x1c81000 0x1000 0x1c82000 0x2000 0x1c84000 0x2000 0x1c86000 0x2000>;
  778. interrupt-controller;
  779. #interrupt-cells = <0x03>;
  780. interrupts = <0x01 0x09 0xf04>;
  781. phandle = <0x01>;
  782. };
  783.  
  784. camera@1cb0000 {
  785. compatible = "allwinner,sun8i-h3-csi";
  786. reg = <0x1cb0000 0x1000>;
  787. interrupts = <0x00 0x54 0x04>;
  788. clocks = <0x03 0x2d 0x03 0x6a 0x03 0x62>;
  789. clock-names = "bus\0mod\0ram";
  790. resets = <0x03 0x1e>;
  791. pinctrl-names = "default";
  792. pinctrl-0 = <0x21>;
  793. status = "disabled";
  794. };
  795.  
  796. hdmi@1ee0000 {
  797. #sound-dai-cells = <0x00>;
  798. compatible = "allwinner,sun8i-h3-dw-hdmi\0allwinner,sun8i-a83t-dw-hdmi";
  799. reg = <0x1ee0000 0x10000>;
  800. reg-io-width = <0x01>;
  801. interrupts = <0x00 0x58 0x04>;
  802. clocks = <0x03 0x2f 0x03 0x70 0x03 0x6f>;
  803. clock-names = "iahb\0isfr\0tmds";
  804. resets = <0x03 0x21>;
  805. reset-names = "ctrl";
  806. phys = <0x22>;
  807. phy-names = "phy";
  808. status = "okay";
  809. phandle = <0x04>;
  810.  
  811. ports {
  812. #address-cells = <0x01>;
  813. #size-cells = <0x00>;
  814.  
  815. port@0 {
  816. reg = <0x00>;
  817.  
  818. endpoint {
  819. remote-endpoint = <0x23>;
  820. phandle = <0x09>;
  821. };
  822. };
  823.  
  824. port@1 {
  825. reg = <0x01>;
  826.  
  827. endpoint {
  828. remote-endpoint = <0x24>;
  829. phandle = <0x37>;
  830. };
  831. };
  832. };
  833. };
  834.  
  835. hdmi-phy@1ef0000 {
  836. compatible = "allwinner,sun8i-h3-hdmi-phy";
  837. reg = <0x1ef0000 0x10000>;
  838. clocks = <0x03 0x2f 0x03 0x70 0x03 0x06>;
  839. clock-names = "bus\0mod\0pll-0";
  840. resets = <0x03 0x20>;
  841. reset-names = "phy";
  842. #phy-cells = <0x00>;
  843. phandle = <0x22>;
  844. };
  845.  
  846. rtc@1f00000 {
  847. reg = <0x1f00000 0x400>;
  848. interrupts = <0x00 0x28 0x04 0x00 0x29 0x04>;
  849. clock-output-names = "osc32k\0osc32k-out\0iosc";
  850. clocks = <0x25>;
  851. #clock-cells = <0x01>;
  852. compatible = "allwinner,sun8i-h3-rtc";
  853. phandle = <0x12>;
  854. };
  855.  
  856. clock@1f01400 {
  857. compatible = "allwinner,sun8i-h3-r-ccu";
  858. reg = <0x1f01400 0x100>;
  859. clocks = <0x11 0x12 0x00 0x12 0x02 0x03 0x09>;
  860. clock-names = "hosc\0losc\0iosc\0pll-periph";
  861. #clock-cells = <0x01>;
  862. #reset-cells = <0x01>;
  863. phandle = <0x26>;
  864. };
  865.  
  866. codec-analog@1f015c0 {
  867. compatible = "allwinner,sun8i-h3-codec-analog";
  868. reg = <0x1f015c0 0x04>;
  869. phandle = <0x19>;
  870. };
  871.  
  872. ir@1f02000 {
  873. compatible = "allwinner,sun6i-a31-ir";
  874. clocks = <0x26 0x04 0x26 0x0b>;
  875. clock-names = "apb\0ir";
  876. resets = <0x26 0x00>;
  877. interrupts = <0x00 0x25 0x04>;
  878. reg = <0x1f02000 0x400>;
  879. status = "okay";
  880. pinctrl-names = "default";
  881. pinctrl-0 = <0x27>;
  882. };
  883.  
  884. i2c@1f02400 {
  885. compatible = "allwinner,sun6i-a31-i2c";
  886. reg = <0x1f02400 0x400>;
  887. interrupts = <0x00 0x2c 0x04>;
  888. pinctrl-names = "default";
  889. pinctrl-0 = <0x28>;
  890. clocks = <0x26 0x09>;
  891. resets = <0x26 0x05>;
  892. status = "okay";
  893. #address-cells = <0x01>;
  894. #size-cells = <0x00>;
  895.  
  896. regulator@65 {
  897. compatible = "silergy,sy8106a";
  898. reg = <0x65>;
  899. regulator-name = "vdd-cpux";
  900. silergy,fixed-microvolt = <0x124f80>;
  901. regulator-min-microvolt = <0xf4240>;
  902. regulator-max-microvolt = <0x13d620>;
  903. regulator-boot-on;
  904. regulator-always-on;
  905. phandle = <0x2f>;
  906. };
  907. };
  908.  
  909. pinctrl@1f02c00 {
  910. compatible = "allwinner,sun8i-h3-r-pinctrl";
  911. reg = <0x1f02c00 0x400>;
  912. interrupts = <0x00 0x2d 0x04>;
  913. clocks = <0x26 0x03 0x11 0x12 0x00>;
  914. clock-names = "apb\0hosc\0losc";
  915. gpio-controller;
  916. #gpio-cells = <0x03>;
  917. interrupt-controller;
  918. #interrupt-cells = <0x03>;
  919. phandle = <0x36>;
  920.  
  921. r-ir-rx-pin {
  922. pins = "PL11";
  923. function = "s_cir_rx";
  924. phandle = <0x27>;
  925. };
  926.  
  927. r-i2c-pins {
  928. pins = "PL0\0PL1";
  929. function = "s_i2c";
  930. phandle = <0x28>;
  931. };
  932.  
  933. r-pwm-pin {
  934. pins = "PL10";
  935. function = "s_pwm";
  936. phandle = <0x29>;
  937. };
  938. };
  939.  
  940. pwm@1f03800 {
  941. compatible = "allwinner,sun8i-h3-pwm";
  942. reg = <0x1f03800 0x08>;
  943. pinctrl-names = "default";
  944. pinctrl-0 = <0x29>;
  945. clocks = <0x11>;
  946. #pwm-cells = <0x03>;
  947. status = "disabled";
  948. };
  949.  
  950. deinterlace@1400000 {
  951. compatible = "allwinner,sun8i-h3-deinterlace";
  952. reg = <0x1400000 0x20000>;
  953. clocks = <0x03 0x2c 0x03 0x68 0x03 0x63>;
  954. clock-names = "bus\0mod\0ram";
  955. resets = <0x03 0x1d>;
  956. interrupts = <0x00 0x5d 0x04>;
  957. interconnects = <0x2a 0x09>;
  958. interconnect-names = "dma-mem";
  959. };
  960.  
  961. system-control@1c00000 {
  962. compatible = "allwinner,sun8i-h3-system-control";
  963. reg = <0x1c00000 0x1000>;
  964. #address-cells = <0x01>;
  965. #size-cells = <0x01>;
  966. ranges;
  967. phandle = <0x13>;
  968.  
  969. sram@1d00000 {
  970. compatible = "mmio-sram";
  971. reg = <0x1d00000 0x80000>;
  972. #address-cells = <0x01>;
  973. #size-cells = <0x01>;
  974. ranges = <0x00 0x1d00000 0x80000>;
  975.  
  976. sram-section@0 {
  977. compatible = "allwinner,sun8i-h3-sram-c1\0allwinner,sun4i-a10-sram-c1";
  978. reg = <0x00 0x80000>;
  979. phandle = <0x2b>;
  980. };
  981. };
  982. };
  983.  
  984. video-codec@1c0e000 {
  985. compatible = "allwinner,sun8i-h3-video-engine";
  986. reg = <0x1c0e000 0x1000>;
  987. clocks = <0x03 0x29 0x03 0x6c 0x03 0x61>;
  988. clock-names = "ahb\0mod\0ram";
  989. resets = <0x03 0x1a>;
  990. interrupts = <0x00 0x3a 0x04>;
  991. allwinner,sram = <0x2b 0x01>;
  992. };
  993.  
  994. crypto@1c15000 {
  995. compatible = "allwinner,sun8i-h3-crypto";
  996. reg = <0x1c15000 0x1000>;
  997. interrupts = <0x00 0x5e 0x04>;
  998. clocks = <0x03 0x14 0x03 0x51>;
  999. clock-names = "bus\0mod";
  1000. resets = <0x03 0x05>;
  1001. };
  1002.  
  1003. gpu@1c40000 {
  1004. compatible = "allwinner,sun8i-h3-mali\0arm,mali-400";
  1005. reg = <0x1c40000 0x10000>;
  1006. interrupts = <0x00 0x61 0x04 0x00 0x62 0x04 0x00 0x63 0x04 0x00 0x64 0x04 0x00 0x66 0x04 0x00 0x67 0x04 0x00 0x65 0x04>;
  1007. interrupt-names = "gp\0gpmmu\0pp0\0ppmmu0\0pp1\0ppmmu1\0pmu";
  1008. clocks = <0x03 0x31 0x03 0x72>;
  1009. clock-names = "bus\0core";
  1010. resets = <0x03 0x23>;
  1011. operating-points-v2 = <0x2c>;
  1012. };
  1013.  
  1014. thermal-sensor@1c25000 {
  1015. compatible = "allwinner,sun8i-h3-ths";
  1016. reg = <0x1c25000 0x400>;
  1017. interrupts = <0x00 0x1f 0x04>;
  1018. resets = <0x03 0x2a>;
  1019. clocks = <0x03 0x37 0x03 0x45>;
  1020. clock-names = "bus\0mod";
  1021. nvmem-cells = <0x2d>;
  1022. nvmem-cell-names = "calibration";
  1023. #thermal-sensor-cells = <0x00>;
  1024. phandle = <0x34>;
  1025. };
  1026. };
  1027.  
  1028. opp_table0 {
  1029. compatible = "operating-points-v2";
  1030. opp-shared;
  1031. phandle = <0x2e>;
  1032.  
  1033. opp-648000000 {
  1034. opp-hz = <0x00 0x269fb200>;
  1035. opp-microvolt = <0xfde80 0xfde80 0x13d620>;
  1036. clock-latency-ns = <0x3b9b0>;
  1037. };
  1038.  
  1039. opp-816000000 {
  1040. opp-hz = <0x00 0x30a32c00>;
  1041. opp-microvolt = <0x10c8e0 0x10c8e0 0x13d620>;
  1042. clock-latency-ns = <0x3b9b0>;
  1043. };
  1044.  
  1045. opp-1008000000 {
  1046. opp-hz = <0x00 0x3c14dc00>;
  1047. opp-microvolt = <0x124f80 0x124f80 0x13d620>;
  1048. clock-latency-ns = <0x3b9b0>;
  1049. };
  1050. };
  1051.  
  1052. cpus {
  1053. #address-cells = <0x01>;
  1054. #size-cells = <0x00>;
  1055.  
  1056. cpu@0 {
  1057. compatible = "arm,cortex-a7";
  1058. device_type = "cpu";
  1059. reg = <0x00>;
  1060. clocks = <0x03 0x0e>;
  1061. clock-names = "cpu";
  1062. operating-points-v2 = <0x2e>;
  1063. #cooling-cells = <0x02>;
  1064. cpu-supply = <0x2f>;
  1065. phandle = <0x30>;
  1066. };
  1067.  
  1068. cpu@1 {
  1069. compatible = "arm,cortex-a7";
  1070. device_type = "cpu";
  1071. reg = <0x01>;
  1072. clocks = <0x03 0x0e>;
  1073. clock-names = "cpu";
  1074. operating-points-v2 = <0x2e>;
  1075. #cooling-cells = <0x02>;
  1076. phandle = <0x31>;
  1077. };
  1078.  
  1079. cpu@2 {
  1080. compatible = "arm,cortex-a7";
  1081. device_type = "cpu";
  1082. reg = <0x02>;
  1083. clocks = <0x03 0x0e>;
  1084. clock-names = "cpu";
  1085. operating-points-v2 = <0x2e>;
  1086. #cooling-cells = <0x02>;
  1087. phandle = <0x32>;
  1088. };
  1089.  
  1090. cpu@3 {
  1091. compatible = "arm,cortex-a7";
  1092. device_type = "cpu";
  1093. reg = <0x03>;
  1094. clocks = <0x03 0x0e>;
  1095. clock-names = "cpu";
  1096. operating-points-v2 = <0x2e>;
  1097. #cooling-cells = <0x02>;
  1098. phandle = <0x33>;
  1099. };
  1100. };
  1101.  
  1102. gpu-opp-table {
  1103. compatible = "operating-points-v2";
  1104. phandle = <0x2c>;
  1105.  
  1106. opp-120000000 {
  1107. opp-hz = <0x00 0x7270e00>;
  1108. };
  1109.  
  1110. opp-312000000 {
  1111. opp-hz = <0x00 0x1298be00>;
  1112. };
  1113.  
  1114. opp-432000000 {
  1115. opp-hz = <0x00 0x19bfcc00>;
  1116. };
  1117.  
  1118. opp-576000000 {
  1119. opp-hz = <0x00 0x22551000>;
  1120. };
  1121. };
  1122.  
  1123. pmu {
  1124. compatible = "arm,cortex-a7-pmu";
  1125. interrupts = <0x00 0x78 0x04 0x00 0x79 0x04 0x00 0x7a 0x04 0x00 0x7b 0x04>;
  1126. interrupt-affinity = <0x30 0x31 0x32 0x33>;
  1127. };
  1128.  
  1129. timer {
  1130. compatible = "arm,armv7-timer";
  1131. interrupts = <0x01 0x0d 0xf08 0x01 0x0e 0xf08 0x01 0x0b 0xf08 0x01 0x0a 0xf08>;
  1132. };
  1133.  
  1134. thermal-zones {
  1135.  
  1136. cpu-thermal {
  1137. polling-delay-passive = <0x00>;
  1138. polling-delay = <0x00>;
  1139. thermal-sensors = <0x34 0x00>;
  1140.  
  1141. trips {
  1142.  
  1143. cpu-hot {
  1144. temperature = <0x13880>;
  1145. hysteresis = <0x7d0>;
  1146. type = "passive";
  1147. phandle = <0x35>;
  1148. };
  1149.  
  1150. cpu-very-hot {
  1151. temperature = <0x186a0>;
  1152. hysteresis = <0x00>;
  1153. type = "critical";
  1154. };
  1155. };
  1156.  
  1157. cooling-maps {
  1158.  
  1159. cpu-hot-limit {
  1160. trip = <0x35>;
  1161. cooling-device = <0x30 0xffffffff 0xffffffff 0x31 0xffffffff 0xffffffff 0x32 0xffffffff 0xffffffff 0x33 0xffffffff 0xffffffff>;
  1162. };
  1163. };
  1164. };
  1165. };
  1166.  
  1167. ahci-5v {
  1168. compatible = "regulator-fixed";
  1169. regulator-name = "ahci-5v";
  1170. regulator-min-microvolt = <0x4c4b40>;
  1171. regulator-max-microvolt = <0x4c4b40>;
  1172. regulator-boot-on;
  1173. enable-active-high;
  1174. gpio = <0x0c 0x01 0x08 0x00>;
  1175. status = "disabled";
  1176. };
  1177.  
  1178. usb0-vbus {
  1179. compatible = "regulator-fixed";
  1180. regulator-name = "usb0-vbus";
  1181. regulator-min-microvolt = <0x4c4b40>;
  1182. regulator-max-microvolt = <0x4c4b40>;
  1183. enable-active-high;
  1184. gpio = <0x36 0x00 0x02 0x00>;
  1185. status = "okay";
  1186. phandle = <0x10>;
  1187. };
  1188.  
  1189. usb1-vbus {
  1190. compatible = "regulator-fixed";
  1191. regulator-name = "usb1-vbus";
  1192. regulator-min-microvolt = <0x4c4b40>;
  1193. regulator-max-microvolt = <0x4c4b40>;
  1194. regulator-boot-on;
  1195. enable-active-high;
  1196. gpio = <0x0c 0x07 0x06 0x00>;
  1197. status = "disabled";
  1198. };
  1199.  
  1200. usb2-vbus {
  1201. compatible = "regulator-fixed";
  1202. regulator-name = "usb2-vbus";
  1203. regulator-min-microvolt = <0x4c4b40>;
  1204. regulator-max-microvolt = <0x4c4b40>;
  1205. regulator-boot-on;
  1206. enable-active-high;
  1207. gpio = <0x0c 0x07 0x03 0x00>;
  1208. status = "disabled";
  1209. };
  1210.  
  1211. vcc3v0 {
  1212. compatible = "regulator-fixed";
  1213. regulator-name = "vcc3v0";
  1214. regulator-min-microvolt = <0x2dc6c0>;
  1215. regulator-max-microvolt = <0x2dc6c0>;
  1216. };
  1217.  
  1218. vcc3v3 {
  1219. compatible = "regulator-fixed";
  1220. regulator-name = "vcc3v3";
  1221. regulator-min-microvolt = <0x325aa0>;
  1222. regulator-max-microvolt = <0x325aa0>;
  1223. phandle = <0x0b>;
  1224. };
  1225.  
  1226. vcc5v0 {
  1227. compatible = "regulator-fixed";
  1228. regulator-name = "vcc5v0";
  1229. regulator-min-microvolt = <0x4c4b40>;
  1230. regulator-max-microvolt = <0x4c4b40>;
  1231. };
  1232.  
  1233. aliases {
  1234. ethernet0 = "/soc/ethernet@1c30000";
  1235. serial0 = "/soc/serial@1c28000";
  1236. ethernet1 = "/soc/mmc@1c10000/sdio_wifi@1";
  1237. };
  1238.  
  1239. connector {
  1240. compatible = "hdmi-connector";
  1241. type = [61 00];
  1242.  
  1243. port {
  1244.  
  1245. endpoint {
  1246. remote-endpoint = <0x37>;
  1247. phandle = <0x24>;
  1248. };
  1249. };
  1250. };
  1251.  
  1252. sound_spdif {
  1253. compatible = "simple-audio-card";
  1254. simple-audio-card,name = "On-board SPDIF";
  1255.  
  1256. simple-audio-card,cpu {
  1257. sound-dai = <&spdif>;
  1258. };
  1259.  
  1260. simple-audio-card,codec {
  1261. sound-dai = <&spdif_out>;
  1262. };
  1263. };
  1264.  
  1265. spdif_out: spdif-out {
  1266. #sound-dai-cells = <0>;
  1267. compatible = "linux,spdif-dit";
  1268. };
  1269.  
  1270.  
  1271. leds {
  1272. compatible = "gpio-leds";
  1273.  
  1274. pwr_led {
  1275. label = "orangepi:green:pwr";
  1276. gpios = <0x36 0x00 0x0a 0x00>;
  1277. default-state = "on";
  1278. };
  1279.  
  1280. status_led {
  1281. label = "orangepi:red:status";
  1282. gpios = <0x0c 0x00 0x0f 0x00>;
  1283. };
  1284. };
  1285.  
  1286. r_gpio_keys {
  1287. compatible = "gpio-keys";
  1288.  
  1289. sw4 {
  1290. label = "sw4";
  1291. linux,code = <0x100>;
  1292. gpios = <0x36 0x00 0x03 0x01>;
  1293. };
  1294. };
  1295. };
RAW Paste Data

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