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  1. #ifndef _SIM_H_
  2. #define _SIM_H_
  3.  
  4.  
  5. #include <stdint.h>
  6. #include <math.h>
  7. #include <stdio.h>
  8. #include <stdlib.h>
  9.  
  10. struct cache{
  11. uint32_t assoc; /* associatividade, 1 para map. direto */
  12. uint32_t block; /* número de bytes por bloco */
  13. uint32_t num_blocks; /* número de blocos por conjunto */
  14. uint32_t lat; /* latência de acesso em ciclos */
  15. };
  16.  
  17.  
  18. struct stats{
  19. unsigned long *hits; /* vetor para cada nível de cache */
  20. unsigned long *misses; /* idem */
  21. unsigned long cycles; /* número total de ciclos da simulação */
  22. };
  23.  
  24. /** Recebe um traço de endereços de memória acessados e simula hierarquia de memória
  25. * @param configs vetor de configurações de caches
  26. * @param num_configs número de níveis de cache
  27. * @param mem_lat latência em ciclos de acesso à memória
  28. * @param filename nome do arquivo de traço (ou null)
  29. * @param stream stream com traço (se filename for null)
  30. * @return estatísticas de simulação
  31. */
  32. struct stats * sim(struct cache * configs, int num_configs,
  33. uint32_t mem_lat, char * filename, char * stream);
  34.  
  35. void setValues(uint32_t* tag, uint32_t* index, uint32_t size,struct cache * configs);
  36. void getValues(uint32_t*tag,uint32_t*index,uint32_t tagsize,uint32_t indexsize, uint32_t end);
  37. int _hash(char * str, int num_blocks, int assoc);
  38. int cacheSize(int assoc, int num_blocks, int block);
  39. void startStats(struct stats * sim);
  40. void LRUstart(uint32_t * Cache, uint32_t size);
  41. int dirMapped(uint32_t * Cache, int tag, int pos, int cycles,char mode,int extra);
  42. int assocMapped(uint32_t * Cache, int tag, int pos, int cycles, char mode,int extra, struct cache * configs);
  43. int getBlockPos(int index,int num_blocks);
  44. int acessCache(struct cache * config,struct stats sim,int * Cache, uint32_t end,int num_configs, uint32_t mem_lat,char mode);
  45.  
  46. uint32_t hex2int(char *hex);
  47.  
  48.  
  49. /* TAG - BLOCK INDEX - OFFSET */
  50.  
  51. int main(){
  52. //testa so mem
  53. /*
  54. char * trace = "R 12345678\nW 90ABCDEF\n";
  55. struct stats * res = sim(NULL, 0, 10, NULL, trace);
  56. */
  57. //testa l1
  58. //char * trace = "R 12345678\nW 90ABCDEF\n";
  59. struct cache mycache = {1, 4, 2, 1};
  60. //struct stats * res = sim(&mycache, 1, 10, NULL, trace);
  61.  
  62. /*char * filename = "filename";
  63. char * trace = "R 12345678\nR 12345678\n";
  64. struct stats * res = sim(&mycache, 1, 10, NULL, trace);
  65. */
  66. struct cache mycache2 = {2, 8, 4, 1};
  67. char * trace3 = "R 12345678\nW 90ABCDEF\nW 00000410\nW 00000324\nW 000003ec\nW 00000410\n";
  68. struct stats * res = sim(&mycache2, 1, 10, NULL, trace3);
  69. return 0;
  70. }
  71.  
  72. struct stats * sim(struct cache * configs, int num_configs, uint32_t mem_lat, char * filename, char * stream){
  73. struct stats *sim = malloc(sizeof(struct stats));
  74. FILE *fp = NULL;// = fopen("C:\\Users\\Laster\\Documents\\Standard\\Estudos\\filename.txt","r");
  75. int size = 0;
  76. uint32_t end, i = 0, bit = 0, full = 0,tag,indexsize,index, tagsize, pos,extra = 0;
  77. char *p = stream, str[11], *q, str1[11], str2[11];
  78.  
  79. printf("test\n");
  80. printf("test\n");
  81. printf("test\n");
  82. if(configs != NULL){
  83. size = cacheSize(configs->assoc,configs->num_blocks,configs->block);
  84. setValues(&tagsize,&indexsize,size, configs);
  85. }
  86.  
  87. startStats(sim);
  88. uint32_t Cache[configs->num_blocks];
  89.  
  90.  
  91.  
  92.  
  93. if(fp != NULL) // TEM ARQUIVO
  94. {
  95. while(fscanf(fp,"%[^\n]\n",str) != EOF)
  96. {
  97. printf("%s\n", str);
  98. }
  99. return NULL;
  100. }
  101. else // USAR STREAM
  102. {
  103. while( *p != '\0'){
  104. while(*p != '\n' && *p != '\0'){ //pega o endereço em string
  105. str[i] = *p;
  106. i++;p++;
  107. }
  108.  
  109. p++;
  110. str[i] = '\0';
  111.  
  112. q = str + 2;
  113. end = hex2int(str);
  114. i = 0;
  115. //getValues(&tag,&index,tagsize,indexsize,end);
  116. if(acessCache(configs,*sim,&Cache,end,num_configs,mem_lat,str[0])){}
  117. /*
  118. if(num_configs == 0){ //ACESSO DIRETO A MEMORIA
  119. (*sim).cycles += mem_lat;
  120. }
  121. else if(num_configs == 1){ //ACESSO L1
  122. //end = _hash(str1,configs->num_blocks,configs->assoc);
  123.  
  124. pos = getBlockPos(index,configs->num_blocks);
  125. printf("\npos=%d\n", pos);
  126. if(configs->assoc == 1){ //mapeando direto
  127. if(dirMapped(Cache,tag,pos,sim->cycles,str[0],extra)){ //hit
  128. sim->cycles += configs->lat;
  129. *(*sim).hits += 1;
  130. }
  131. else{//miss
  132. if(extra == 1){(*sim).cycles += mem_lat;} //if it was a miss in a writtenblock then writeback policy
  133. (*sim).cycles += 1;
  134. (*sim).cycles += mem_lat;
  135. *(*sim).misses += 1;
  136. }
  137. extra = 0;
  138. }
  139. else if(configs->assoc == configs->num_blocks){ //assoaciatividade completa
  140.  
  141. }
  142. else{ //associativo
  143. if(assocMapped(Cache,tag,pos,sim->cycles,str[0],extra,configs)){
  144. sim->cycles += configs->lat;
  145. *(*sim).hits += 1;
  146. }
  147. else{//miss
  148. if(extra == 1){(*sim).cycles += mem_lat;} //if it was a miss in a writtenblock then writeback policy
  149. (*sim).cycles += 1;
  150. (*sim).cycles += mem_lat;
  151. *(*sim).misses += 1;
  152. }
  153. }
  154. }
  155. else{ //ACESSO l2
  156.  
  157. }*/
  158. }
  159. }
  160. return sim;
  161. }
  162. int assocMapped(uint32_t * Cache, int tag, int pos, int cycles, char mode,int extra, struct cache * configs){
  163. uint32_t tTag, timer = cycles, V, D, aux, i, LRUpos = cycles;
  164. for(i=0;i<configs->assoc;i++){ //laço para encontrar um bloco vazio
  165. V = Cache[pos] >> 31;
  166. D = Cache[pos] << 1 >> 31;
  167. aux = tag; aux <<= 10;
  168. timer = cycles;
  169. aux = aux | timer; //aux OR timer, coloca tag e timer da LRU nos bits
  170.  
  171. if(V == 0){ //checks if its not inicialized, else verifies if its a hit
  172. V = 1;
  173. if(mode == 'R'){
  174. Cache[pos] = 1;
  175. Cache[pos] = Cache[pos] << 31;
  176. }
  177. else{
  178. Cache[pos] = 3;
  179. Cache[pos] = Cache[pos] << 30;
  180. }
  181.  
  182. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  183. printf("%d", Cache[pos]);
  184. return 0; //return miss
  185. }
  186. else{
  187. tTag = Cache[pos] << 2; tTag = tTag >> 12;
  188. if(tag == tTag){ // HIT
  189. if(mode == 'R'){
  190. Cache[pos] = 1; Cache[pos] = Cache[pos] << 31;
  191. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  192. }
  193. else{
  194. Cache[pos] = 3; Cache[pos] = Cache[pos] << 30;
  195. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  196. }
  197. Cache[pos] = Cache[pos] >> 10; //Limpa LRU
  198. Cache[pos] = Cache[pos] << 10;
  199. Cache[pos] = Cache[pos] | cycles; //atualiza LRU
  200. return 1; //return hit
  201. }
  202. if(LRUpos < timer){ //finds the least recently used block in case theres no free block
  203. LRUpos = pos;
  204. }
  205. }
  206. pos += configs->num_blocks;
  207. }
  208. //at this point theres no empty block, and no hits, so we use LRU policy
  209. pos = LRUpos;
  210. D = Cache[pos] << 1 >> 31;
  211. V = Cache[pos] >> 31;
  212. aux = tag; aux <<= 10;
  213. timer = cycles;
  214. aux = aux | timer; //aux OR timer, coloca tag e timer da LRU nos bits
  215.  
  216. if(D == 1){ extra = 1; }
  217. if(mode == 'R'){
  218. Cache[pos] = 1; Cache[pos] = Cache[pos] << 31;
  219. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  220. }
  221. else{
  222. Cache[pos] = 3; Cache[pos] = Cache[pos] << 30;
  223. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  224. }
  225. Cache[pos] = Cache[pos] >> 10; //Limpa LRU
  226. Cache[pos] = Cache[pos] << 10;
  227. Cache[pos] = Cache[pos] | cycles; //atualiza LRU
  228. return 0;
  229. }
  230. int dirMapped(uint32_t * Cache, int tag, int pos, int cycles, char mode,int extra){
  231. uint32_t tTag, timer, V, D, aux;
  232. D = Cache[pos] << 1 >> 31;
  233. V = Cache[pos] >> 31;
  234. aux = tag; aux <<= 10;
  235. timer = cycles;
  236. aux = aux | timer; //aux OR timer, coloca tag e timer da LRU nos bits
  237.  
  238. if(V == 0){ //bloco nao utilizado antes, logo miss
  239. V = 1;
  240. if(mode == 'R')
  241. Cache[pos] = 1; //Cache[pos] = Cache[pos] << 30;
  242. else
  243. Cache[pos] = 3; Cache[pos] = Cache[pos] << 30;
  244. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  245. return 0; //return miss
  246. }
  247. else{ //
  248. timer = Cache[pos] << 22; timer = timer >> 22;
  249. tTag = Cache[pos] << 2; tTag = tTag >> 12;
  250. if(tag == tTag){ // HIT
  251. if(mode == 'R'){
  252. Cache[pos] = 1; Cache[pos] = Cache[pos] << 31;
  253. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  254. }
  255. else{
  256. Cache[pos] = 3; Cache[pos] = Cache[pos] << 30;
  257. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  258. }
  259. Cache[pos] = Cache[pos] >> 10; //Limpa LRU
  260. Cache[pos] = Cache[pos] << 10;
  261. Cache[pos] = Cache[pos] | cycles; //atualiza LRU
  262. return 1; //return hit
  263. }
  264. else{ //MISS
  265. if(D == 1){ extra = 1; }
  266. if(mode == 'R'){
  267. Cache[pos] = 1; Cache[pos] = Cache[pos] << 31;
  268. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  269. }
  270. else{
  271. Cache[pos] = 3; Cache[pos] = Cache[pos] << 30;
  272. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  273. }
  274. Cache[pos] = Cache[pos] >> 10; //Limpa LRU
  275. Cache[pos] = Cache[pos] << 10;
  276. Cache[pos] = Cache[pos] | cycles; //atualiza LRU
  277. }
  278. }
  279. return 0;
  280. }
  281.  
  282. //this function is taken from: https://stackoverflow.com/questions/10156409/convert-hex-string-char-to-int
  283. //
  284. uint32_t hex2int(char *hex) {
  285. uint32_t val = 0;
  286. while (*hex) {
  287. // get current character then increment
  288. uint8_t byte = *hex++;
  289. // transform hex character to the 4bit equivalent number, using the ascii table indexes
  290. if (byte >= '0' && byte <= '9') byte = byte - '0';
  291. else if (byte >= 'a' && byte <='f') byte = byte - 'a' + 10;
  292. else if (byte >= 'A' && byte <='F') byte = byte - 'A' + 10;
  293. // shift 4 to make space for new digit, and add the 4 bits of the new digit
  294. val = (val << 4) | (byte & 0xF);
  295. }
  296. return val;
  297. }
  298. void getValues(uint32_t*tag,uint32_t*index,uint32_t tagsize,uint32_t indexsize,uint32_t end){
  299. *tag = end >> (32-tagsize); //32 - (tagsize + indexsize) -> calculo do OFFSET
  300. *index = end << tagsize >> 32 - (tagsize + indexsize) + tagsize;
  301. return;
  302. }
  303. int getBlockPos(int index,int num_blocks){
  304. return index % num_blocks;
  305. }
  306.  
  307. void setValues(uint32_t* tag, uint32_t* index, uint32_t size,struct cache * configs){
  308. int offset = (int) log2((double)configs->block);
  309. *index = (int) log2((double)configs->num_blocks);
  310. *tag = 32 - (*index + offset);
  311. }
  312.  
  313. /*
  314. setStrings(str1,str2,stream);
  315. void setStrings(char * str1, char * str2, char * stream){ //Funcao para separar os endereços de entrada
  316. int i; char *p;
  317. p = stream;
  318. for(i=0; *p != '\n'; p++,i++){
  319. str1[i] = *p;
  320. }
  321. p = stream+11;
  322. for(i=0; *p != '\n'; p++,i++){
  323. str2[i] = *p;
  324. }
  325. str1[i] = '\0';
  326. str2[i] = '\0';
  327. return;
  328. }*/
  329.  
  330. int _hash(char * str, int num_blocks, int assoc){
  331. int i, res, target_block;
  332. char *p, op[3];
  333. char q = str + 7;
  334. for(i=0;i<3;i++,p++){
  335. op[i] = *p;
  336. }
  337. res = (int) strtol(op, NULL, 16); //converts string to long int, third arg selects base.
  338.  
  339.  
  340. target_block = res % assoc;
  341. res = res % num_blocks;
  342. if(assoc == 1)
  343. return res;
  344. else
  345. return target_block;
  346. }
  347.  
  348. int cacheSize(int assoc, int num_blocks, int block){
  349. printf("here");
  350. return assoc * (4*block) * num_blocks;
  351. }
  352.  
  353. void startStats(struct stats * sim){
  354. //sim->cycles = malloc(sizeof(unsigned long));
  355. (*sim).hits = malloc(sizeof(unsigned long));
  356. (*sim).misses = malloc(sizeof(unsigned long));
  357. (*sim).cycles = 0;
  358. *(*sim).hits = 0;
  359. *(*sim).misses = 0;
  360. return;
  361. }
  362.  
  363.  
  364. void LRUstart(uint32_t * Cache, uint32_t size){
  365. uint32_t i;
  366. for(i = 0 ; i<size ; i++){
  367. Cache[i] = i;
  368. }
  369. }
  370.  
  371. int acessCache(struct cache * config,struct stats sim,int * Cache, uint32_t end,int num_configs, uint32_t mem_lat,char mode){
  372. uint32_t tag,index,tagsize,indexsize,size,pos,extra;
  373.  
  374. setValues(&tagsize,&indexsize,size, configs);
  375. getValues(&tag,&index,tagsize,indexsize,end);
  376.  
  377. if(num_configs == 0){ //ACESSO DIRETO A MEMORIA
  378. (*sim).cycles += mem_lat;
  379. }
  380. else if(num_configs == 1){ //ACESSO L1
  381. //end = _hash(str1,configs->num_blocks,configs->assoc);
  382.  
  383. pos = getBlockPos(index,configs->num_blocks);
  384. printf("\npos=%d\n", pos);
  385. if(configs->assoc == 1){ //mapeando direto
  386. if(dirMapped(Cache,tag,pos,sim->cycles,mode,extra)){ //hit
  387. sim->cycles += configs->lat;
  388. *(*sim).hits += 1;
  389. }
  390. else{//miss
  391. if(extra == 1){(*sim).cycles += mem_lat;} //if it was a miss in a writtenblock then writeback policy
  392. (*sim).cycles += 1;
  393. (*sim).cycles += mem_lat;
  394. *(*sim).misses += 1;
  395. }
  396. extra = 0;
  397. }
  398. else if(configs->assoc == configs->num_blocks){ //assoaciatividade completa
  399.  
  400. }
  401. else{ //associativo
  402. if(assocMapped(Cache,tag,pos,sim->cycles,mode,extra,configs)){
  403. sim->cycles += configs->lat;
  404. *(*sim).hits += 1;
  405. }
  406. else{//miss
  407. if(extra == 1){(*sim).cycles += mem_lat;} //if it was a miss in a writtenblock then writeback policy
  408. (*sim).cycles += 1;
  409. (*sim).cycles += mem_lat;
  410. *(*sim).misses += 1;
  411. }
  412. }
  413. }
  414.  
  415.  
  416.  
  417.  
  418.  
  419.  
  420.  
  421. #endif // _SIM_H_
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