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Nov 13th, 2019
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  1. Warning (125092): Tcl Script File counter_bus_bux.qip not found
  2. Info (125063): set_global_assignment -name QIP_FILE counter_bus_bux.qip
  3. Info (125063): set_global_assignment -name QIP_FILE counter_bus_bux.qip
  4. Warning (20028): Parallel compilation is not licensed and has been disabled
  5. Warning (125092): Tcl Script File counter_bus_bux.qip not found
  6. Info (125063): set_global_assignment -name QIP_FILE counter_bus_bux.qip
  7. Info (125063): set_global_assignment -name QIP_FILE counter_bus_bux.qip
  8. Warning (20028): Parallel compilation is not licensed and has been disabled
  9. Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
  10. Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
  11. Critical Warning (332012): Synopsys Design Constraints File file not found: 'my_first_fpga.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
  12. Warning (125092): Tcl Script File counter_bus_bux.qip not found
  13. Info (125063): set_global_assignment -name QIP_FILE counter_bus_bux.qip
  14. Info (125063): set_global_assignment -name QIP_FILE counter_bus_bux.qip
  15. Warning (20028): Parallel compilation is not licensed and has been disabled
  16. Critical Warning (332012): Synopsys Design Constraints File file not found: 'my_first_fpga.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
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