Programmable Wait State Generator

RE = Rising Edge
FE = Falling Edge

I'm sorry if this whole description of a circuit is confusingly written i tried my best to write down how i think this thing could work but i kept rewriting different parts of it over and over again, so it'll likely require a few reads.


>>>>Programmable Wait State Generator:
>>>>Main Idea:

the whole thing uses a "Slot" System, where each slot consists of atleast 3 registers.
more Registers can be added too, for example the order/use of all 8 bits inside the first Control Register are reserved.
so if you need more control bits you need to add an extra Control Register.
it's recommended that all Registers of the same type are directly after one another and the overall order is always Control, Start, End.

(x refers to the slot number)
(y refers to the Register number, if there are more than 1 of a Register Type Present)
Cyx - Control Register
Syx - Starting Address Register
Eyx - Ending Address Register

so for example the 2nd Starting Address Register of slot 4 would be called "S14"

if the CPU Accesses a Memory Location that is equal to or between the contents of the Sx and Ex Registers
or the opposite if the "invert" bit in the Cx Register is set (bit 1)
and the "Slot enable" bit is set in the Cx Register (bit 0)
then the ~RDY output will be pulled low on the next RE for some amount of clock cycles (+ 1) given by the Cx Register (bits 2-7)
once all the cycles have passed, or the ~DONE input has been pulled low, ~RDY will be pulled high at the next RE.

Slots with a higher number have a higher priority


>>>>Register Selection:

Accessing Registers is pretty simple. one IO Address is used for a Write-Only "Selection Register" that selects the slot which has it's Register placed in memory after itself.
for example if the Selection Register is placed at 0xDF00 in Memory (and the devices uses a 4 register setup) then memory will look like this after selecting any slot.

0xDF00 - Selection Register
0xDF01 - Control Register 0 (Slot x)
0xDF02 - Control Register 1 (Slot x)
0xDF03 - Starting Address Register (Slot x)
0xDF04 - Ending Address Register (Slot x)

this allows for a total of 256 Slots. (assuming an 8 bit Selection Register)


>>>>Address Register Details:

The total width of the Address Registers and how the bits are ordered depend on what is required in the system.
And also what resources are available (TTL Logic ICs, Small CPLD, Large FPGA, etc)
essentically there are 3 ways to Address the Wait State Range.

1. The full thing:
Where the Address Registers have the same width as the Address Bus of the CPU (16/24 bit for 65C02/65816)
This gives the you best Control as a Slot can select any range from a single Address to the whole Address Space.
Downside is that it's rather expensive and requires a lot of Registers and logic (especially for the 65816).

CPU: xxxxxxxx xxxxxxxx xxxxxxxx
Sx : ssssssss ssssssss ssssssss
Ex : eeeeeeee eeeeeeee eeeeeeee

2. Slicing off upper bits:
Where the Address Register's width is smaller than the Address Bus of the CPU.
for example on a 65C02, 8 bit Address Registers can represent the bottom 8 bits of the Address Bus, and the upper 8 bits are taken
from an extra Control Register.
this Limits the total range of a Slot to the current 256 byte page it is placed in by the 2nd Control Register.
but it allows for individual Addresses to be selected and saves some resources.
this is useful if you only have a Small CPLD or not a lot of slow multi-page large IO Devices.

CPU: xxxxxxxx xxxxxxxx
Sx : cccccccc ssssssss (bottom 8 bits: Starting Address Register, upper 8 bits: 2nd Control Register)
Ex : cccccccc eeeeeeee (bottom 8 bits: Ending Address Register, upper 8 bits: 2nd Control Register)

3. Slicing off lower bits:
Same idea as 2. but instead of the Addresss Registers being aligned with the bottom n bits of the Address Bus they are aligned with the upper n bits.
using the 65C02 as an example, the Address Registers are 8 bit wide but this time represent the upper 8 bits of the Address Bus, the lower 8 bits are simply ignored. this means the range is always in steps of 256 bytes, making it impossible to select individual Addresses.
This seems useful for selecting Memory (Slow ROM, DRAM, etc) or if you have a lot of similarly slow IO Devices in a single area.

CPU: xxxxxxxx xxxxxxxx
Sx : ssssssss 00000000 (bottom 8 bits: 0, upper 8 bits: Starting Address Register)
Ex : eeeeeeee 00000000 (bottom 8 bits: 0, upper 8 bits: Ending Address Register)


>>>>Conclusion:

Overall i think a Universal/Progammable Wait State Generator like this could be useful for any PC-like System that allows you to add a lot of extra IO Devices, where it's not guaranteed that the IO Device will be fast enough or what the exact speed of the CPU at any given time is going to be.
so instead of each IO Device having to implement it's own Wait State circuit, you just have one of these Wait State Generators with the CPU and then just slow down each device using Software/Drivers instead.