----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    19:47:34 03/25/2017
-- Design Name:
-- Module Name:    Mode - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Mode is
Port (
      clk : in  STD_LOGIC;
        mode : in  STD_LOGIC;
        stateChange : in  STD_LOGIC;
        password : in STD_LOGIC_VECTOR(8 downto 0);
        output1 : out STD_LOGIC_VECTOR(15 downto 0)
      );
end Mode;

architecture Behavioral of Mode is
TYPE State_type IS (A,B,C,D,insertPattern);
--TYPE State1_type IS (insertPattern);
SIGNAL State : State_Type;
--SIGNAL State1 : State1_Type;
SIGNAL vector1: STD_LOGIC_VECTOR (15 downto 0) := "1111110111001011";
--A  the old password state
--B the new password state
--C the new password 2 state
--D done
begin
process(clk)
variable firstEntry : STD_LOGIC := '0';
variable old: STD_LOGIC_VECTOR (8 downto 0) := "000000000";
variable new2: STD_LOGIC_VECTOR (8 downto 0) := "000000000";
variable vector: STD_LOGIC_VECTOR (15 downto 0) := "1111110111001011";
begin
if(rising_edge(clk))then
 --if (stateChange='1') then--programming mode
--  vector:="1111110111001011"; --old FDCB
  if(mode ='1' and vector= "1111110111001011"and stateChange='1' )then
  State <= A;  --old.
  end if;
  case State is
    when A =>    --the old state
	  vector:="1111110111001011"; --old FDCB
     if (firstEntry = '0'and password = old) then
       firstEntry:='1';
		 vector:="1010100110000001"; --new1 A981
		 State<= B;
      elsif (firstEntry = '1'and password = old) then
         old := password;   --di mmkn malhash lazma
		   vector:="1010100110000001"; --new1 A981
			State <=B;
      else
		vector:="1111110111001011"; --old FDCB
		State <=A;
     end if;

     when B =>  ---new 1
	  if(stateChange='1' and mode ='1')then
	  --vector:="1010100110000001"; --new1 A981
	  vector:="1010100110000010"; --new2 A982
     old:=password;
		State <=C;
		end if;
    when C =>
	 --vector:="1010100110000010"; --new2 A982
	  if(stateChange='1' and mode ='1')then
      if (old =password) then
       new2 := password;--3lshan el lock fe el operating mode
		  vector:="1011110110101001";--done BDA9
       State<=D;
      else
       State<=A;
      end if;
		end if;

    when D =>
     if (mode ='1' and stateChange='1')then
	    vector:="1011110110101001";--done BDA9
       State <=D;
		 end if;
		if(mode ='0'and stateChange='0')then
		  vector:= "1100110101110110";--LOCK CD76
		  State <= insertPattern;
		  end if;

		when insertPattern =>
		if(mode ='0'and stateChange='1')then
        if(new2 = password)then-- new
          vector := "1101010110011010";--OPEn D59A
        else
        vector := "1111100101000100";--Err F944-----------------------------------------
        State<=insertPattern;
        end if;
     end if;
   end case;
  end if;
--end if;
vector1<=vector;
end process;
output1<=vector1;

end Behavioral;