--DISPLAY

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity DISPLAY is
    port(
        CLK_i : in STD_LOGIC;
        RST_i : in STD_LOGIC;
        SW : in STD_LOGIC_vector (7 downto 0);
        BTN : in STD_LOGIC_vector (3 downto 0);
        AN : out STD_LOGIC_vector (3 downto 0);
        SEG : out STD_LOGIC_vector (7 downto 0)
    );
end DISPLAY;

architecture Behavioral of DISPLAY is

    signal BTN_ktory : STD_LOGIC_vector (3 downto 0) := "0000";
    signal DGT_teraz : STD_LOGIC_vector (31 downto 0) := "11111111111111111111111111111111";
    signal CLK_1kHz : STD_LOGIC;

   component dzielnik_czt is
    port (
          CLK_i: in  STD_LOGIC;
        RST_i  : in  STD_LOGIC;
        led7 : out STD_LOGIC
        );
    end component;

    component wyswietlacz
        port (CLK_i : in  STD_LOGIC;
           RST_i : in  STD_LOGIC;
           DGT_i : in  STD_LOGIC_VECTOR (31 downto 0);
           AN : out  STD_LOGIC_VECTOR (3 downto 0);
           SEG : out  STD_LOGIC_VECTOR (7 downto 0));
   end component;


    function zamiana(SW: STD_LOGIC_VECTOR (3 downto 0)) return STD_LOGIC_VECTOR is
        begin
        case SW is
              when "0000" => return "0000001"; -- 0
              when "0001" => return "1001111"; -- 1
              when "0010" => return "0010010"; -- 2
              when "0011" => return "0000110"; -- 3
              when "0100" => return "1001100"; -- 4
              when "0101" => return "0100100"; -- 5
              when "0110" => return "0100000"; -- 6
              when "0111" => return "0001111"; -- 7
              when "1000" => return "0000000"; -- 8
              when "1001" => return "0000100"; -- 9
              when "1010" => return "0000010"; -- a
              when "1011" => return "1100000"; -- b
              when "1100" => return "0110001"; -- C
              when "1101" => return "1000010"; -- d
              when "1110" => return "0110000"; -- E
              when "1111" => return "0111000"; -- F
        end case;
    end function zamiana;


    begin
    dzielonko: dzielnik_czt port map(
                                      CLK_i => CLK_i,
                             RST_i => '0',
                             led7 => CLK_1kHz);

    wyswietlanko: wyswietlacz port map(
                                      CLK_i => CLK_1kHz,
                             RST_i => '0',
                             DGT_i => DGT_teraz,
                             AN => AN,
                             SEG => SEG);

    ustawianie : process(CLK_i)
      begin
        if(rising_edge(CLK_i)) then
            BTN_ktory <= BTN;            --wyswietlanie wybranej liczby
                DGT_teraz(0) <= not SW(4);   --dodawanie kropek
                DGT_teraz(8) <= not SW(5);
                DGT_teraz(16) <= not SW(6);
                DGT_teraz(24) <= not SW(7);


            if(BTN_ktory = "1110") then
                DGT_teraz <= zamiana(SW(3 downto 0));

            elsif(BTN_ktory = "1101") then
                DGT_teraz <= zamiana(SW(3 downto 0));

            elsif(BTN_ktory = "1011") then
                DGT_teraz <= zamiana(SW(3 downto 0));

            elsif(BTN_ktory = "0111") then
                DGT_teraz <= zamiana(SW(3 downto 0));

            else DGT_teraz<= DGT_teraz;

            end if;
        end if;

    end process;

end Behavioral;






--dzielnik_czt



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dzielnik_czt is
    port (
        CLK_i : in  STD_LOGIC;
        RST_i  : in  STD_LOGIC;
        led7 : out STD_LOGIC
    );
end dzielnik_czt;

architecture behavioral of dzielnik_czt is

    constant N : integer := 50000;
     signal wynik: STD_LOGIC := '0';
     signal licz : integer range 0 to (N - 1);

        begin

         dzielnik_czestot: process (RST_i, CLK_i)
                begin
              if (RST_i = '1') then
                    wynik <= '0';
                    licz <= 0;
              elsif (rising_edge(CLK_i)) then
                          licz <= licz + 1;
                                if( N = 2) then
                                    wynik <= not(wynik);
                                    licz <= 0;
                                elsif(licz = (N/2)) then
                                    wynik <= '1';
                                elsif(licz = (N - 1)) then
                                    wynik <= '0';
                                    licz <= 0;
                                end if;
              end if;
            end process dzielnik_czestot;

    led7 <= wynik;

end Behavioral;






--wyswietlacz



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity wyswietlacz is
    port(
        CLK_i : in STD_LOGIC;
        RST_i : in STD_LOGIC;
        DGT_i : in STD_LOGIC_vector (31 downto 0);
        AN : out STD_LOGIC_vector (3 downto 0);
        SEG : out STD_LOGIC_vector (7 downto 0)
    );
end wyswietlacz;



architecture Behavioral of wyswietlacz is
    signal aktywny_AN: STD_LOGIC_VECTOR (3 downto 0) := "1111";

begin
    process(CLK_i, RST_i, DGT_i, aktywny_AN)

         begin
                if(RST_i = '1') then
                    AN <= "0000";
                    SEG <= "00000000";
                elsif(rising_edge(CLK_i)) then
                    case aktywny_AN is
                        when "0000" => aktywny_AN <= "0111";
                        when "0111" => aktywny_AN <= "1011";
                        when "1011" => aktywny_AN <= "1101";
                        when "1101" => aktywny_AN <= "1110";
                        when "1110" => aktywny_AN <= "0111";
                        when others => aktywny_AN <= "0111";
                    end case;

                    case aktywny_AN is
                        when "0111" => SEG <= DGT_i(31 downto 24);
                        when "1011" => SEG <= DGT_i(23 downto 16);
                        when "1101" => SEG <= DGT_i(15 downto 8);
                        when "1110" => SEG <= DGT_i(7 downto 0);
                        when others => SEG <= "00000000";
                    end case;

              end if;
        AN <= aktywny_AN;
    end process;

end Behavioral;