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  1. /* Automatically generated by nMigen 0.3.dev153+gb86acdc. Do not edit. */
  2. /* Generated by Yosys 0.9+2406 (git sha1 aafaeb66, clang 10.0.0 -fPIC -Os) */
  3.  
  4. (* \nmigen.hierarchy  = "top.top.blink" *)
  5. (* generator = "nMigen" *)
  6. module blink(pixel_rst, pixel_clk, o_led);
  7.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/blink.py:15" *)
  8.   wire [28:0] \$1 ;
  9.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/blink.py:15" *)
  10.   wire [28:0] \$2 ;
  11.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/blink.py:14" *)
  12.   reg [27:0] R_counter = 28'h0000000;
  13.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/blink.py:14" *)
  14.   reg [27:0] \R_counter$next ;
  15.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/blink.py:7" *)
  16.   output [7:0] o_led;
  17.   (* src = "top_vgatest.py:101" *)
  18.   input pixel_clk;
  19.   (* src = "top_vgatest.py:101" *)
  20.   input pixel_rst;
  21.   assign \$2  = R_counter + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/blink.py:15" *) 1'h1;
  22.   always @(posedge pixel_clk)
  23.       R_counter <= \R_counter$next ;
  24.   always @* begin
  25.     \R_counter$next  = \$1 [27:0];
  26.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  27.     casez (pixel_rst)
  28.       1'h1:
  29.           \R_counter$next  = 28'h0000000;
  30.     endcase
  31.   end
  32.   assign \$1  = \$2 ;
  33.   assign o_led = R_counter[27:20];
  34. endmodule
  35.  
  36. (* \nmigen.hierarchy  = "top.top.ecp5pll" *)
  37. (* generator = "nMigen" *)
  38. module ecp5pll(clk25_0__io, pixel_clk, shift_clk, clk);
  39.   (* src = "top_vgatest.py:100" *)
  40.   output clk;
  41.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  42.   input clk25_0__io;
  43.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/ecp5pll.py:26" *)
  44.   wire locked;
  45.   (* src = "top_vgatest.py:101" *)
  46.   output pixel_clk;
  47.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/ecp5pll.py:25" *)
  48.   wire reset;
  49.   (* src = "top_vgatest.py:102" *)
  50.   output shift_clk;
  51.   (* FREQUENCY_PIN_CLKI = "25.0" *)
  52.   (* ICP_CURRENT = "6" *)
  53.   (* LPF_RESISTOR = "16" *)
  54.   (* MFG_ENABLE_FILTEROPAMP = "1" *)
  55.   (* MFG_GMCREF_SEL = "2" *)
  56.   EHXPLLL #(
  57.     .CLKFB_DIV(32'd113),
  58.     .CLKI_DIV(32'd4),
  59.     .CLKOP_CPHASE(32'd28),
  60.     .CLKOP_DIV(32'd28),
  61.     .CLKOP_ENABLE("ENABLED"),
  62.     .CLKOP_FPHASE(32'd0),
  63.     .CLKOS2_CPHASE(32'd2),
  64.     .CLKOS2_DIV(32'd2),
  65.     .CLKOS2_ENABLE("ENABLED"),
  66.     .CLKOS2_FPHASE(32'd0),
  67.     .CLKOS3_DIV(32'd1),
  68.     .CLKOS3_ENABLE("ENABLED"),
  69.     .CLKOS_CPHASE(32'd10),
  70.     .CLKOS_DIV(32'd10),
  71.     .CLKOS_ENABLE("ENABLED"),
  72.     .CLKOS_FPHASE(32'd0),
  73.     .FEEDBK_PATH("INT_OS3")
  74.   ) \U$$0  (
  75.     .CLKI(clk25_0__io),
  76.     .CLKOP(clk),
  77.     .CLKOS(pixel_clk),
  78.     .CLKOS2(shift_clk),
  79.     .LOCK(locked),
  80.     .RST(reset)
  81.   );
  82.   assign reset = 1'h0;
  83. endmodule
  84.  
  85. (* \nmigen.hierarchy  = "top.pin_button_down_0" *)
  86. (* generator = "nMigen" *)
  87. module pin_button_down_0(button_down_0__io, button_down_0__i);
  88.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  89.   output button_down_0__i;
  90.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  91.   input button_down_0__io;
  92.   IB button_down_0_0 (
  93.     .I(button_down_0__io),
  94.     .O(button_down_0__i)
  95.   );
  96. endmodule
  97.  
  98. (* \nmigen.hierarchy  = "top.pin_button_fire_0" *)
  99. (* generator = "nMigen" *)
  100. module pin_button_fire_0(button_fire_0__io, button_fire_0__i);
  101.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  102.   output button_fire_0__i;
  103.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  104.   input button_fire_0__io;
  105.   IB button_fire_0_0 (
  106.     .I(button_fire_0__io),
  107.     .O(button_fire_0__i)
  108.   );
  109. endmodule
  110.  
  111. (* \nmigen.hierarchy  = "top.pin_button_fire_1" *)
  112. (* generator = "nMigen" *)
  113. module pin_button_fire_1(button_fire_1__io, button_fire_1__i);
  114.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  115.   output button_fire_1__i;
  116.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  117.   input button_fire_1__io;
  118.   IB button_fire_1_0 (
  119.     .I(button_fire_1__io),
  120.     .O(button_fire_1__i)
  121.   );
  122. endmodule
  123.  
  124. (* \nmigen.hierarchy  = "top.pin_button_left_0" *)
  125. (* generator = "nMigen" *)
  126. module pin_button_left_0(button_left_0__io, button_left_0__i);
  127.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  128.   output button_left_0__i;
  129.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  130.   input button_left_0__io;
  131.   IB button_left_0_0 (
  132.     .I(button_left_0__io),
  133.     .O(button_left_0__i)
  134.   );
  135. endmodule
  136.  
  137. (* \nmigen.hierarchy  = "top.pin_button_pwr_0" *)
  138. (* generator = "nMigen" *)
  139. module pin_button_pwr_0(button_pwr_0__io, button_pwr_0__i);
  140.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/vendor/lattice_ecp5.py:447" *)
  141.   wire \$1 ;
  142.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  143.   output button_pwr_0__i;
  144.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/vendor/lattice_ecp5.py:446" *)
  145.   wire button_pwr_0__i_n;
  146.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  147.   input button_pwr_0__io;
  148.   assign \$1  = ~ (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/vendor/lattice_ecp5.py:447" *) button_pwr_0__i_n;
  149.   IB button_pwr_0_0 (
  150.     .I(button_pwr_0__io),
  151.     .O(button_pwr_0__i_n)
  152.   );
  153.   assign button_pwr_0__i = \$1 ;
  154. endmodule
  155.  
  156. (* \nmigen.hierarchy  = "top.pin_button_right_0" *)
  157. (* generator = "nMigen" *)
  158. module pin_button_right_0(button_right_0__io, button_right_0__i);
  159.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  160.   output button_right_0__i;
  161.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  162.   input button_right_0__io;
  163.   IB button_right_0_0 (
  164.     .I(button_right_0__io),
  165.     .O(button_right_0__i)
  166.   );
  167. endmodule
  168.  
  169. (* \nmigen.hierarchy  = "top.pin_button_up_0" *)
  170. (* generator = "nMigen" *)
  171. module pin_button_up_0(button_up_0__io, button_up_0__i);
  172.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  173.   output button_up_0__i;
  174.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  175.   input button_up_0__io;
  176.   IB button_up_0_0 (
  177.     .I(button_up_0__io),
  178.     .O(button_up_0__i)
  179.   );
  180. endmodule
  181.  
  182. (* \nmigen.hierarchy  = "top.pin_hdmi_0__cec" *)
  183. (* generator = "nMigen" *)
  184. module pin_hdmi_0__cec(hdmi_0__cec__io);
  185.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/vendor/lattice_ecp5.py:513" *)
  186.   wire \$1 ;
  187.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  188.   wire hdmi_0__cec__i;
  189.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  190.   inout hdmi_0__cec__io;
  191.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  192.   wire hdmi_0__cec__o;
  193.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  194.   wire hdmi_0__cec__oe;
  195.   assign \$1  = ~ (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/vendor/lattice_ecp5.py:513" *) hdmi_0__cec__oe;
  196.   BB hdmi_0__cec_0 (
  197.     .B(hdmi_0__cec__io),
  198.     .I(hdmi_0__cec__o),
  199.     .O(hdmi_0__cec__i),
  200.     .T(\$1 )
  201.   );
  202.   assign hdmi_0__cec__oe = 1'h0;
  203.   assign hdmi_0__cec__o = 1'h0;
  204. endmodule
  205.  
  206. (* \nmigen.hierarchy  = "top.pin_hdmi_0__eth" *)
  207. (* generator = "nMigen" *)
  208. module pin_hdmi_0__eth(hdmi_0__eth__p);
  209.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/vendor/lattice_ecp5.py:513" *)
  210.   wire \$1 ;
  211.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  212.   wire hdmi_0__eth__i;
  213.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  214.   wire hdmi_0__eth__o;
  215.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  216.   wire hdmi_0__eth__oe;
  217.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:139" *)
  218.   inout hdmi_0__eth__p;
  219.   assign \$1  = ~ (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/vendor/lattice_ecp5.py:513" *) hdmi_0__eth__oe;
  220.   BB hdmi_0__eth_0 (
  221.     .B(hdmi_0__eth__p),
  222.     .I(hdmi_0__eth__o),
  223.     .O(hdmi_0__eth__i),
  224.     .T(\$1 )
  225.   );
  226.   assign hdmi_0__eth__oe = 1'h0;
  227.   assign hdmi_0__eth__o = 1'h0;
  228. endmodule
  229.  
  230. (* \nmigen.hierarchy  = "top.pin_hdmi_0__scl" *)
  231. (* generator = "nMigen" *)
  232. module pin_hdmi_0__scl(hdmi_0__scl__io);
  233.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/vendor/lattice_ecp5.py:513" *)
  234.   wire \$1 ;
  235.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  236.   wire hdmi_0__scl__i;
  237.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  238.   inout hdmi_0__scl__io;
  239.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  240.   wire hdmi_0__scl__o;
  241.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  242.   wire hdmi_0__scl__oe;
  243.   assign \$1  = ~ (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/vendor/lattice_ecp5.py:513" *) hdmi_0__scl__oe;
  244.   BB hdmi_0__scl_0 (
  245.     .B(hdmi_0__scl__io),
  246.     .I(hdmi_0__scl__o),
  247.     .O(hdmi_0__scl__i),
  248.     .T(\$1 )
  249.   );
  250.   assign hdmi_0__scl__oe = 1'h0;
  251.   assign hdmi_0__scl__o = 1'h0;
  252. endmodule
  253.  
  254. (* \nmigen.hierarchy  = "top.pin_hdmi_0__sda" *)
  255. (* generator = "nMigen" *)
  256. module pin_hdmi_0__sda(hdmi_0__sda__io);
  257.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/vendor/lattice_ecp5.py:513" *)
  258.   wire \$1 ;
  259.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  260.   wire hdmi_0__sda__i;
  261.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  262.   inout hdmi_0__sda__io;
  263.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  264.   wire hdmi_0__sda__o;
  265.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  266.   wire hdmi_0__sda__oe;
  267.   assign \$1  = ~ (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/vendor/lattice_ecp5.py:513" *) hdmi_0__sda__oe;
  268.   BB hdmi_0__sda_0 (
  269.     .B(hdmi_0__sda__io),
  270.     .I(hdmi_0__sda__o),
  271.     .O(hdmi_0__sda__i),
  272.     .T(\$1 )
  273.   );
  274.   assign hdmi_0__sda__oe = 1'h0;
  275.   assign hdmi_0__sda__o = 1'h0;
  276. endmodule
  277.  
  278. (* \nmigen.hierarchy  = "top.pin_led_0" *)
  279. (* generator = "nMigen" *)
  280. module pin_led_0(led_0__io, led_0__o);
  281.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  282.   output led_0__io;
  283.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  284.   input led_0__o;
  285.   OB led_0_0 (
  286.     .I(led_0__o),
  287.     .O(led_0__io)
  288.   );
  289. endmodule
  290.  
  291. (* \nmigen.hierarchy  = "top.pin_led_1" *)
  292. (* generator = "nMigen" *)
  293. module pin_led_1(led_1__io, led_1__o);
  294.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  295.   output led_1__io;
  296.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  297.   input led_1__o;
  298.   OB led_1_0 (
  299.     .I(led_1__o),
  300.     .O(led_1__io)
  301.   );
  302. endmodule
  303.  
  304. (* \nmigen.hierarchy  = "top.pin_led_2" *)
  305. (* generator = "nMigen" *)
  306. module pin_led_2(led_2__io, led_2__o);
  307.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  308.   output led_2__io;
  309.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  310.   input led_2__o;
  311.   OB led_2_0 (
  312.     .I(led_2__o),
  313.     .O(led_2__io)
  314.   );
  315. endmodule
  316.  
  317. (* \nmigen.hierarchy  = "top.pin_led_3" *)
  318. (* generator = "nMigen" *)
  319. module pin_led_3(led_3__io, led_3__o);
  320.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  321.   output led_3__io;
  322.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  323.   input led_3__o;
  324.   OB led_3_0 (
  325.     .I(led_3__o),
  326.     .O(led_3__io)
  327.   );
  328. endmodule
  329.  
  330. (* \nmigen.hierarchy  = "top.pin_led_4" *)
  331. (* generator = "nMigen" *)
  332. module pin_led_4(led_4__io, led_4__o);
  333.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  334.   output led_4__io;
  335.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  336.   input led_4__o;
  337.   OB led_4_0 (
  338.     .I(led_4__o),
  339.     .O(led_4__io)
  340.   );
  341. endmodule
  342.  
  343. (* \nmigen.hierarchy  = "top.pin_led_5" *)
  344. (* generator = "nMigen" *)
  345. module pin_led_5(led_5__io, led_5__o);
  346.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  347.   output led_5__io;
  348.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  349.   input led_5__o;
  350.   OB led_5_0 (
  351.     .I(led_5__o),
  352.     .O(led_5__io)
  353.   );
  354. endmodule
  355.  
  356. (* \nmigen.hierarchy  = "top.pin_led_6" *)
  357. (* generator = "nMigen" *)
  358. module pin_led_6(led_6__io, led_6__o);
  359.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  360.   output led_6__io;
  361.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  362.   input led_6__o;
  363.   OB led_6_0 (
  364.     .I(led_6__o),
  365.     .O(led_6__io)
  366.   );
  367. endmodule
  368.  
  369. (* \nmigen.hierarchy  = "top.pin_led_7" *)
  370. (* generator = "nMigen" *)
  371. module pin_led_7(led_7__io, led_7__o);
  372.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  373.   output led_7__io;
  374.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  375.   input led_7__o;
  376.   OB led_7_0 (
  377.     .I(led_7__o),
  378.     .O(led_7__io)
  379.   );
  380. endmodule
  381.  
  382. (* \nmigen.hierarchy  = "top.pin_program_0" *)
  383. (* generator = "nMigen" *)
  384. module pin_program_0(program_0__io);
  385.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/vendor/lattice_ecp5.py:455" *)
  386.   wire \$1 ;
  387.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  388.   output program_0__io;
  389.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  390.   wire program_0__o;
  391.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/vendor/lattice_ecp5.py:454" *)
  392.   wire program_0__o_n;
  393.   assign \$1  = ~ (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/vendor/lattice_ecp5.py:455" *) program_0__o;
  394.   OB program_0_0 (
  395.     .I(program_0__o_n),
  396.     .O(program_0__io)
  397.   );
  398.   assign program_0__o = 1'h0;
  399.   assign program_0__o_n = \$1 ;
  400. endmodule
  401.  
  402. (* \nmigen.hierarchy  = "top" *)
  403. (* top =  1  *)
  404. (* generator = "nMigen" *)
  405. module top(hdmi_0__scl__io, hdmi_0__sda__io, hdmi_0__eth__p, led_0__io, led_1__io, led_2__io, led_3__io, led_4__io, led_5__io, led_6__io, led_7__io, button_pwr_0__io, button_fire_0__io, button_fire_1__io, button_up_0__io, button_down_0__io, button_left_0__io, button_right_0__io, hdmi_0__clk__p, hdmi_0__d__p, program_0__io, clk25_0__io, hdmi_0__cec__io);
  406.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  407.   input button_down_0__io;
  408.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  409.   input button_fire_0__io;
  410.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  411.   input button_fire_1__io;
  412.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  413.   input button_left_0__io;
  414.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  415.   input button_pwr_0__io;
  416.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  417.   input button_right_0__io;
  418.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  419.   input button_up_0__io;
  420.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  421.   input clk25_0__io;
  422.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  423.   inout hdmi_0__cec__io;
  424.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:139" *)
  425.   output hdmi_0__clk__p;
  426.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:139" *)
  427.   output [2:0] hdmi_0__d__p;
  428.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:139" *)
  429.   inout hdmi_0__eth__p;
  430.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  431.   inout hdmi_0__scl__io;
  432.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  433.   inout hdmi_0__sda__io;
  434.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  435.   output led_0__io;
  436.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  437.   output led_1__io;
  438.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  439.   output led_2__io;
  440.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  441.   output led_3__io;
  442.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  443.   output led_4__io;
  444.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  445.   output led_5__io;
  446.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  447.   output led_6__io;
  448.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  449.   output led_7__io;
  450.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  451.   wire pin_button_down_0_button_down_0__i;
  452.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  453.   wire pin_button_fire_0_button_fire_0__i;
  454.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  455.   wire pin_button_fire_1_button_fire_1__i;
  456.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  457.   wire pin_button_left_0_button_left_0__i;
  458.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  459.   wire pin_button_pwr_0_button_pwr_0__i;
  460.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  461.   wire pin_button_right_0_button_right_0__i;
  462.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  463.   wire pin_button_up_0_button_up_0__i;
  464.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  465.   wire pin_led_0_led_0__o;
  466.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  467.   wire pin_led_1_led_1__o;
  468.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  469.   wire pin_led_2_led_2__o;
  470.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  471.   wire pin_led_3_led_3__o;
  472.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  473.   wire pin_led_4_led_4__o;
  474.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  475.   wire pin_led_5_led_5__o;
  476.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  477.   wire pin_led_6_led_6__o;
  478.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  479.   wire pin_led_7_led_7__o;
  480.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  481.   output program_0__io;
  482.   (* src = "top_vgatest.py:60" *)
  483.   wire [6:0] top_i_btn;
  484.   (* src = "top_vgatest.py:62" *)
  485.   wire [3:0] top_o_gpdi_dp;
  486.   (* src = "top_vgatest.py:61" *)
  487.   wire [7:0] top_o_led;
  488.   (* src = "top_vgatest.py:63" *)
  489.   wire top_o_user_programn;
  490.   pin_button_down_0 pin_button_down_0 (
  491.     .button_down_0__i(pin_button_down_0_button_down_0__i),
  492.     .button_down_0__io(button_down_0__io)
  493.   );
  494.   pin_button_fire_0 pin_button_fire_0 (
  495.     .button_fire_0__i(pin_button_fire_0_button_fire_0__i),
  496.     .button_fire_0__io(button_fire_0__io)
  497.   );
  498.   pin_button_fire_1 pin_button_fire_1 (
  499.     .button_fire_1__i(pin_button_fire_1_button_fire_1__i),
  500.     .button_fire_1__io(button_fire_1__io)
  501.   );
  502.   pin_button_left_0 pin_button_left_0 (
  503.     .button_left_0__i(pin_button_left_0_button_left_0__i),
  504.     .button_left_0__io(button_left_0__io)
  505.   );
  506.   pin_button_pwr_0 pin_button_pwr_0 (
  507.     .button_pwr_0__i(pin_button_pwr_0_button_pwr_0__i),
  508.     .button_pwr_0__io(button_pwr_0__io)
  509.   );
  510.   pin_button_right_0 pin_button_right_0 (
  511.     .button_right_0__i(pin_button_right_0_button_right_0__i),
  512.     .button_right_0__io(button_right_0__io)
  513.   );
  514.   pin_button_up_0 pin_button_up_0 (
  515.     .button_up_0__i(pin_button_up_0_button_up_0__i),
  516.     .button_up_0__io(button_up_0__io)
  517.   );
  518.   pin_hdmi_0__cec pin_hdmi_0__cec (
  519.     .hdmi_0__cec__io(hdmi_0__cec__io)
  520.   );
  521.   pin_hdmi_0__eth pin_hdmi_0__eth (
  522.     .hdmi_0__eth__p(hdmi_0__eth__p)
  523.   );
  524.   pin_hdmi_0__scl pin_hdmi_0__scl (
  525.     .hdmi_0__scl__io(hdmi_0__scl__io)
  526.   );
  527.   pin_hdmi_0__sda pin_hdmi_0__sda (
  528.     .hdmi_0__sda__io(hdmi_0__sda__io)
  529.   );
  530.   pin_led_0 pin_led_0 (
  531.     .led_0__io(led_0__io),
  532.     .led_0__o(pin_led_0_led_0__o)
  533.   );
  534.   pin_led_1 pin_led_1 (
  535.     .led_1__io(led_1__io),
  536.     .led_1__o(pin_led_1_led_1__o)
  537.   );
  538.   pin_led_2 pin_led_2 (
  539.     .led_2__io(led_2__io),
  540.     .led_2__o(pin_led_2_led_2__o)
  541.   );
  542.   pin_led_3 pin_led_3 (
  543.     .led_3__io(led_3__io),
  544.     .led_3__o(pin_led_3_led_3__o)
  545.   );
  546.   pin_led_4 pin_led_4 (
  547.     .led_4__io(led_4__io),
  548.     .led_4__o(pin_led_4_led_4__o)
  549.   );
  550.   pin_led_5 pin_led_5 (
  551.     .led_5__io(led_5__io),
  552.     .led_5__o(pin_led_5_led_5__o)
  553.   );
  554.   pin_led_6 pin_led_6 (
  555.     .led_6__io(led_6__io),
  556.     .led_6__o(pin_led_6_led_6__o)
  557.   );
  558.   pin_led_7 pin_led_7 (
  559.     .led_7__io(led_7__io),
  560.     .led_7__o(pin_led_7_led_7__o)
  561.   );
  562.   pin_program_0 pin_program_0 (
  563.     .program_0__io(program_0__io)
  564.   );
  565.   \top$1  top (
  566.     .clk25_0__io(clk25_0__io),
  567.     .i_btn(top_i_btn),
  568.     .o_gpdi_dp(top_o_gpdi_dp),
  569.     .o_led(top_o_led),
  570.     .o_user_programn(top_o_user_programn)
  571.   );
  572.   assign hdmi_0__clk__p = top_o_gpdi_dp[3];
  573.   assign hdmi_0__d__p[2] = top_o_gpdi_dp[2];
  574.   assign hdmi_0__d__p[1] = top_o_gpdi_dp[1];
  575.   assign hdmi_0__d__p[0] = top_o_gpdi_dp[0];
  576.   assign top_i_btn[6] = pin_button_right_0_button_right_0__i;
  577.   assign top_i_btn[5] = pin_button_left_0_button_left_0__i;
  578.   assign top_i_btn[4] = pin_button_down_0_button_down_0__i;
  579.   assign top_i_btn[3] = pin_button_up_0_button_up_0__i;
  580.   assign top_i_btn[2] = pin_button_fire_1_button_fire_1__i;
  581.   assign top_i_btn[1] = pin_button_fire_0_button_fire_0__i;
  582.   assign top_i_btn[0] = pin_button_pwr_0_button_pwr_0__i;
  583.   assign pin_led_7_led_7__o = top_o_led[7];
  584.   assign pin_led_6_led_6__o = top_o_led[6];
  585.   assign pin_led_5_led_5__o = top_o_led[5];
  586.   assign pin_led_4_led_4__o = top_o_user_programn;
  587.   assign pin_led_3_led_3__o = top_o_led[3];
  588.   assign pin_led_2_led_2__o = top_o_led[2];
  589.   assign pin_led_1_led_1__o = top_o_led[1];
  590.   assign pin_led_0_led_0__o = top_o_led[0];
  591. endmodule
  592.  
  593. (* \nmigen.hierarchy  = "top.top" *)
  594. (* generator = "nMigen" *)
  595. module \top$1 (i_btn, o_gpdi_dp, o_user_programn, clk25_0__io, o_led);
  596.   (* src = "top_vgatest.py:97" *)
  597.   wire \$11 ;
  598.   (* src = "top_vgatest.py:97" *)
  599.   wire \$13 ;
  600.   (* src = "top_vgatest.py:95" *)
  601.   wire \$4 ;
  602.   (* src = "top_vgatest.py:96" *)
  603.   wire [20:0] \$6 ;
  604.   (* src = "top_vgatest.py:96" *)
  605.   wire [20:0] \$7 ;
  606.   (* src = "top_vgatest.py:97" *)
  607.   wire \$9 ;
  608.   (* src = "top_vgatest.py:149" *)
  609.   wire [1:0] \$signal ;
  610.   (* src = "top_vgatest.py:149" *)
  611.   wire [1:0] \$signal$1 ;
  612.   (* src = "top_vgatest.py:149" *)
  613.   wire [1:0] \$signal$2 ;
  614.   (* src = "top_vgatest.py:149" *)
  615.   wire [1:0] \$signal$3 ;
  616.   (* src = "top_vgatest.py:94" *)
  617.   reg [19:0] R_delay_reload = 20'h00000;
  618.   (* src = "top_vgatest.py:94" *)
  619.   reg [19:0] \R_delay_reload$next ;
  620.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/blink.py:7" *)
  621.   wire [7:0] blink_o_led;
  622.   (* src = "top_vgatest.py:100" *)
  623.   wire clk;
  624.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  625.   input clk25_0__io;
  626.   (* src = "top_vgatest.py:166" *)
  627.   wire [7:0] countblink;
  628.   (* src = "top_vgatest.py:101" *)
  629.   wire ecp5pll_pixel_clk;
  630.   (* src = "top_vgatest.py:102" *)
  631.   wire ecp5pll_shift_clk;
  632.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:33" *)
  633.   wire [7:0] i_b;
  634.   (* src = "top_vgatest.py:60" *)
  635.   input [6:0] i_btn;
  636.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:32" *)
  637.   wire [7:0] i_g;
  638.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:31" *)
  639.   wire [7:0] i_r;
  640.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:30" *)
  641.   wire i_test_picture;
  642.   (* src = "top_vgatest.py:62" *)
  643.   output [3:0] o_gpdi_dp;
  644.   (* src = "top_vgatest.py:61" *)
  645.   output [7:0] o_led;
  646.   (* src = "top_vgatest.py:63" *)
  647.   output o_user_programn;
  648.   (* src = "top_vgatest.py:64" *)
  649.   wire o_wifi_gpio0;
  650.   (* src = "top_vgatest.py:100" *)
  651.   wire rst;
  652.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:17" *)
  653.   wire vga2dvid_i_blank;
  654.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:16" *)
  655.   wire [7:0] vga2dvid_i_blue;
  656.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:15" *)
  657.   wire [7:0] vga2dvid_i_green;
  658.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:18" *)
  659.   wire vga2dvid_i_hsync;
  660.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:14" *)
  661.   wire [7:0] vga2dvid_i_red;
  662.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:19" *)
  663.   wire vga2dvid_i_vsync;
  664.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:27" *)
  665.   wire [1:0] vga2dvid_o_blue;
  666.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:28" *)
  667.   wire [1:0] vga2dvid_o_clk;
  668.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:26" *)
  669.   wire [1:0] vga2dvid_o_green;
  670.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:25" *)
  671.   wire [1:0] vga2dvid_o_red;
  672.   (* src = "top_vgatest.py:117" *)
  673.   wire [7:0] vga_b;
  674.   (* src = "top_vgatest.py:120" *)
  675.   wire vga_blank;
  676.   (* src = "top_vgatest.py:116" *)
  677.   wire [7:0] vga_g;
  678.   (* src = "top_vgatest.py:118" *)
  679.   wire vga_hsync;
  680.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:29" *)
  681.   wire vga_i_clk_en;
  682.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:39" *)
  683.   wire [7:0] vga_o_vga_b;
  684.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:43" *)
  685.   wire vga_o_vga_blank;
  686.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:38" *)
  687.   wire [7:0] vga_o_vga_g;
  688.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:40" *)
  689.   wire vga_o_vga_hsync;
  690.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:37" *)
  691.   wire [7:0] vga_o_vga_r;
  692.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:41" *)
  693.   wire vga_o_vga_vsync;
  694.   (* src = "top_vgatest.py:101" *)
  695.   wire vga_pixel_rst;
  696.   (* src = "top_vgatest.py:115" *)
  697.   wire [7:0] vga_r;
  698.   (* src = "top_vgatest.py:119" *)
  699.   wire vga_vsync;
  700.   assign \$9  = ~ (* src = "top_vgatest.py:97" *) i_btn[0];
  701.   assign \$11  = ~ (* src = "top_vgatest.py:97" *) R_delay_reload[19];
  702.   assign \$13  = \$9  | (* src = "top_vgatest.py:97" *) \$11 ;
  703.   assign \$4  = R_delay_reload[19] == (* src = "top_vgatest.py:95" *) 1'h0;
  704.   assign \$7  = R_delay_reload + (* src = "top_vgatest.py:96" *) 1'h1;
  705.   always @(posedge clk)
  706.       R_delay_reload <= \R_delay_reload$next ;
  707.   blink blink (
  708.     .o_led(blink_o_led),
  709.     .pixel_clk(ecp5pll_pixel_clk),
  710.     .pixel_rst(vga_pixel_rst)
  711.   );
  712.   ODDRX1F ddr0_blue (
  713.     .D0(\$signal$3 [0]),
  714.     .D1(\$signal$3 [1]),
  715.     .Q(o_gpdi_dp[0]),
  716.     .RST(1'h0),
  717.     .SCLK(ecp5pll_shift_clk)
  718.   );
  719.   ODDRX1F ddr0_clock (
  720.     .D0(\$signal [0]),
  721.     .D1(\$signal [1]),
  722.     .Q(o_gpdi_dp[3]),
  723.     .RST(1'h0),
  724.     .SCLK(ecp5pll_shift_clk)
  725.   );
  726.   ODDRX1F ddr0_green (
  727.     .D0(\$signal$2 [0]),
  728.     .D1(\$signal$2 [1]),
  729.     .Q(o_gpdi_dp[1]),
  730.     .RST(1'h0),
  731.     .SCLK(ecp5pll_shift_clk)
  732.   );
  733.   ODDRX1F ddr0_red (
  734.     .D0(\$signal$1 [0]),
  735.     .D1(\$signal$1 [1]),
  736.     .Q(o_gpdi_dp[2]),
  737.     .RST(1'h0),
  738.     .SCLK(ecp5pll_shift_clk)
  739.   );
  740.   ecp5pll ecp5pll (
  741.     .clk(clk),
  742.     .clk25_0__io(clk25_0__io),
  743.     .pixel_clk(ecp5pll_pixel_clk),
  744.     .shift_clk(ecp5pll_shift_clk)
  745.   );
  746.   vga vga (
  747.     .i_clk_en(vga_i_clk_en),
  748.     .o_vga_b(vga_o_vga_b),
  749.     .o_vga_blank(vga_o_vga_blank),
  750.     .o_vga_g(vga_o_vga_g),
  751.     .o_vga_hsync(vga_o_vga_hsync),
  752.     .o_vga_r(vga_o_vga_r),
  753.     .o_vga_vsync(vga_o_vga_vsync),
  754.     .pixel_clk(ecp5pll_pixel_clk),
  755.     .pixel_rst(vga_pixel_rst)
  756.   );
  757.   vga2dvid vga2dvid (
  758.     .i_blank(vga2dvid_i_blank),
  759.     .i_blue(vga2dvid_i_blue),
  760.     .i_green(vga2dvid_i_green),
  761.     .i_hsync(vga2dvid_i_hsync),
  762.     .i_red(vga2dvid_i_red),
  763.     .i_vsync(vga2dvid_i_vsync),
  764.     .o_blue(vga2dvid_o_blue),
  765.     .o_clk(vga2dvid_o_clk),
  766.     .o_green(vga2dvid_o_green),
  767.     .o_red(vga2dvid_o_red),
  768.     .pixel_clk(ecp5pll_pixel_clk),
  769.     .pixel_rst(vga_pixel_rst),
  770.     .shift_clk(ecp5pll_shift_clk)
  771.   );
  772.   always @* begin
  773.     \R_delay_reload$next  = R_delay_reload;
  774.     (* src = "top_vgatest.py:95" *)
  775.     casez (\$4 )
  776.       /* src = "top_vgatest.py:95" */
  777.       1'h1:
  778.           \R_delay_reload$next  = \$6 [19:0];
  779.     endcase
  780.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  781.     casez (rst)
  782.       1'h1:
  783.           \R_delay_reload$next  = 20'h00000;
  784.     endcase
  785.   end
  786.   assign \$6  = \$7 ;
  787.   assign rst = 1'h0;
  788.   assign vga_pixel_rst = 1'h0;
  789.   assign o_led[2] = vga_blank;
  790.   assign o_led[1] = vga_hsync;
  791.   assign o_led[0] = vga_vsync;
  792.   assign o_led[7:6] = countblink[7:6];
  793.   assign o_led[5:3] = 3'h0;
  794.   assign countblink = blink_o_led;
  795.   assign \$signal$3  = vga2dvid_o_blue;
  796.   assign \$signal$2  = vga2dvid_o_green;
  797.   assign \$signal$1  = vga2dvid_o_red;
  798.   assign \$signal  = vga2dvid_o_clk;
  799.   assign vga2dvid_i_blank = vga_blank;
  800.   assign vga2dvid_i_vsync = vga_vsync;
  801.   assign vga2dvid_i_hsync = vga_hsync;
  802.   assign vga2dvid_i_blue = vga_b;
  803.   assign vga2dvid_i_green = vga_g;
  804.   assign vga2dvid_i_red = vga_r;
  805.   assign vga_blank = vga_o_vga_blank;
  806.   assign vga_vsync = vga_o_vga_vsync;
  807.   assign vga_hsync = vga_o_vga_hsync;
  808.   assign vga_b = vga_o_vga_b;
  809.   assign vga_g = vga_o_vga_g;
  810.   assign vga_r = vga_o_vga_r;
  811.   assign i_b = 8'h00;
  812.   assign i_g = 8'h00;
  813.   assign i_r = 8'h00;
  814.   assign i_test_picture = 1'h1;
  815.   assign vga_i_clk_en = 1'h1;
  816.   assign o_user_programn = \$13 ;
  817.   assign o_wifi_gpio0 = i_btn[0];
  818. endmodule
  819.  
  820. (* \nmigen.hierarchy  = "top.top.vga2dvid.u21" *)
  821. (* generator = "nMigen" *)
  822. module u21(pixel_clk, i_data, i_c, i_blank, o_encoded, pixel_rst);
  823.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:25" *)
  824.   wire \$1 ;
  825.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  826.   wire \$101 ;
  827.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  828.   wire \$103 ;
  829.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  830.   wire \$105 ;
  831.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  832.   wire \$107 ;
  833.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  834.   wire \$109 ;
  835.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:30" *)
  836.   wire \$11 ;
  837.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  838.   wire \$111 ;
  839.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  840.   wire \$113 ;
  841.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  842.   wire \$115 ;
  843.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  844.   wire \$117 ;
  845.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  846.   wire \$119 ;
  847.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:97" *)
  848.   wire [9:0] \$121 ;
  849.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  850.   wire \$123 ;
  851.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  852.   wire \$125 ;
  853.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  854.   wire \$127 ;
  855.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  856.   wire \$129 ;
  857.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:31" *)
  858.   wire \$13 ;
  859.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  860.   wire \$131 ;
  861.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  862.   wire \$133 ;
  863.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  864.   wire \$135 ;
  865.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  866.   wire \$137 ;
  867.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  868.   wire \$139 ;
  869.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  870.   wire \$141 ;
  871.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:98" *)
  872.   wire [4:0] \$143 ;
  873.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:98" *)
  874.   wire [4:0] \$144 ;
  875.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:101" *)
  876.   wire [4:0] \$146 ;
  877.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:101" *)
  878.   wire [4:0] \$147 ;
  879.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *)
  880.   wire [5:0] \$149 ;
  881.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *)
  882.   wire \$15 ;
  883.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *)
  884.   wire [4:0] \$150 ;
  885.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *)
  886.   wire [5:0] \$152 ;
  887.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *)
  888.   wire [5:0] \$154 ;
  889.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *)
  890.   wire [4:0] \$155 ;
  891.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *)
  892.   wire [5:0] \$157 ;
  893.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *)
  894.   wire \$16 ;
  895.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *)
  896.   wire \$19 ;
  897.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *)
  898.   wire \$20 ;
  899.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *)
  900.   wire \$23 ;
  901.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *)
  902.   wire \$24 ;
  903.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *)
  904.   wire \$27 ;
  905.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *)
  906.   wire \$28 ;
  907.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:26" *)
  908.   wire \$3 ;
  909.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *)
  910.   wire \$31 ;
  911.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *)
  912.   wire \$32 ;
  913.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *)
  914.   wire \$35 ;
  915.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *)
  916.   wire \$36 ;
  917.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *)
  918.   wire \$39 ;
  919.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *)
  920.   wire \$40 ;
  921.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  922.   wire [8:0] \$43 ;
  923.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  924.   wire [1:0] \$44 ;
  925.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  926.   wire [2:0] \$46 ;
  927.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  928.   wire [3:0] \$48 ;
  929.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:27" *)
  930.   wire \$5 ;
  931.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  932.   wire [4:0] \$50 ;
  933.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  934.   wire [5:0] \$52 ;
  935.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  936.   wire [6:0] \$54 ;
  937.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  938.   wire [7:0] \$56 ;
  939.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  940.   wire [8:0] \$58 ;
  941.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  942.   wire \$60 ;
  943.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  944.   wire \$62 ;
  945.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  946.   wire \$64 ;
  947.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  948.   wire \$66 ;
  949.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  950.   wire \$68 ;
  951.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:28" *)
  952.   wire \$7 ;
  953.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  954.   wire \$70 ;
  955.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  956.   wire \$72 ;
  957.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  958.   wire \$74 ;
  959.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  960.   wire \$76 ;
  961.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  962.   wire \$78 ;
  963.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:63" *)
  964.   wire [8:0] \$80 ;
  965.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:66" *)
  966.   wire [8:0] \$82 ;
  967.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  968.   wire [11:0] \$84 ;
  969.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  970.   wire [4:0] \$85 ;
  971.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  972.   wire [5:0] \$87 ;
  973.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  974.   wire [6:0] \$89 ;
  975.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:29" *)
  976.   wire \$9 ;
  977.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  978.   wire [7:0] \$91 ;
  979.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  980.   wire [8:0] \$93 ;
  981.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  982.   wire [9:0] \$95 ;
  983.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  984.   wire [10:0] \$97 ;
  985.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  986.   wire [11:0] \$99 ;
  987.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:18" *)
  988.   reg [8:0] data_word;
  989.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:20" *)
  990.   wire [3:0] data_word_disparity;
  991.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:19" *)
  992.   reg [8:0] data_word_inv;
  993.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:21" *)
  994.   reg [3:0] dc_bias = 4'h0;
  995.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:21" *)
  996.   reg [3:0] \dc_bias$next ;
  997.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:9" *)
  998.   input i_blank;
  999.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:8" *)
  1000.   input [1:0] i_c;
  1001.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:7" *)
  1002.   input [7:0] i_data;
  1003.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:10" *)
  1004.   output [9:0] o_encoded;
  1005.   reg [9:0] o_encoded = 10'h000;
  1006.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:10" *)
  1007.   reg [9:0] \o_encoded$next ;
  1008.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:17" *)
  1009.   wire [3:0] ones;
  1010.   (* src = "top_vgatest.py:101" *)
  1011.   input pixel_clk;
  1012.   (* src = "top_vgatest.py:101" *)
  1013.   input pixel_rst;
  1014.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:16" *)
  1015.   wire [8:0] xnored;
  1016.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:15" *)
  1017.   wire [8:0] xored;
  1018.   assign \$9  = i_data[5] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:29" *) xored[4];
  1019.   assign \$99  = \$97  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[7];
  1020.   assign \$101  = dc_bias == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  1021.   assign \$103  = data_word_disparity == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  1022.   assign \$105  = \$101  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) \$103 ;
  1023.   assign \$107  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  1024.   assign \$109  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  1025.   assign \$111  = \$107  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$109 ;
  1026.   assign \$113  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  1027.   assign \$115  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  1028.   assign \$117  = \$113  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) \$115 ;
  1029.   assign \$11  = i_data[6] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:30" *) xored[5];
  1030.   assign \$119  = \$111  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$117 ;
  1031.   assign \$121  = + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:97" *) { 1'h1, data_word[7:0] };
  1032.   assign \$123  = dc_bias == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  1033.   assign \$125  = data_word_disparity == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  1034.   assign \$127  = \$123  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) \$125 ;
  1035.   assign \$129  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  1036.   assign \$131  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  1037.   assign \$133  = \$129  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$131 ;
  1038.   assign \$135  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  1039.   assign \$137  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  1040.   assign \$13  = i_data[7] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:31" *) xored[6];
  1041.   assign \$139  = \$135  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) \$137 ;
  1042.   assign \$141  = \$133  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$139 ;
  1043.   assign \$144  = dc_bias + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:98" *) data_word_disparity;
  1044.   assign \$147  = dc_bias - (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:101" *) data_word_disparity;
  1045.   assign \$150  = dc_bias + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *) data_word[8];
  1046.   assign \$152  = \$150  - (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *) data_word_disparity;
  1047.   assign \$155  = dc_bias - (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *) data_word_inv[8];
  1048.   assign \$157  = \$155  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *) data_word_disparity;
  1049.   assign \$16  = i_data[1] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *) xnored[0];
  1050.   assign \$15  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *) \$16 ;
  1051.   assign \$1  = i_data[1] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:25" *) xored[0];
  1052.   assign \$20  = i_data[2] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *) xnored[1];
  1053.   assign \$19  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *) \$20 ;
  1054.   assign \$24  = i_data[3] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *) xnored[2];
  1055.   assign \$23  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *) \$24 ;
  1056.   assign \$28  = i_data[4] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *) xnored[3];
  1057.   assign \$27  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *) \$28 ;
  1058.   assign \$32  = i_data[5] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *) xnored[4];
  1059.   assign \$31  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *) \$32 ;
  1060.   assign \$36  = i_data[6] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *) xnored[5];
  1061.   assign \$35  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *) \$36 ;
  1062.   assign \$3  = i_data[2] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:26" *) xored[1];
  1063.   assign \$40  = i_data[7] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *) xnored[6];
  1064.   assign \$39  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *) \$40 ;
  1065.   assign \$44  = 1'h0 + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[0];
  1066.   assign \$46  = \$44  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[1];
  1067.   assign \$48  = \$46  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[2];
  1068.   assign \$50  = \$48  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[3];
  1069.   assign \$52  = \$50  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[4];
  1070.   assign \$54  = \$52  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[5];
  1071.   assign \$56  = \$54  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[6];
  1072.   assign \$58  = \$56  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[7];
  1073.   assign \$5  = i_data[3] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:27" *) xored[2];
  1074.   assign \$60  = ones > (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  1075.   assign \$62  = ones == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  1076.   assign \$64  = i_data[0] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 1'h0;
  1077.   assign \$66  = \$62  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$64 ;
  1078.   assign \$68  = \$60  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$66 ;
  1079.   assign \$70  = ones > (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  1080.   assign \$72  = ones == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  1081.   assign \$74  = i_data[0] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 1'h0;
  1082.   assign \$76  = \$72  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$74 ;
  1083.   assign \$78  = \$70  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$76 ;
  1084.   assign \$7  = i_data[4] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:28" *) xored[3];
  1085.   assign \$80  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:63" *) xnored;
  1086.   assign \$82  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:66" *) xored;
  1087.   assign \$85  = 4'hc + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[0];
  1088.   assign \$87  = \$85  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[1];
  1089.   assign \$89  = \$87  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[2];
  1090.   assign \$91  = \$89  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[3];
  1091.   assign \$93  = \$91  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[4];
  1092.   assign \$95  = \$93  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[5];
  1093.   assign \$97  = \$95  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[6];
  1094.   always @(posedge pixel_clk)
  1095.       dc_bias <= \dc_bias$next ;
  1096.   always @(posedge pixel_clk)
  1097.       o_encoded <= \o_encoded$next ;
  1098.   always @* begin
  1099.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1100.     casez (\$68 )
  1101.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" */
  1102.       1'h1:
  1103.           data_word = xnored;
  1104.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:64" */
  1105.       default:
  1106.           data_word = xored;
  1107.     endcase
  1108.   end
  1109.   always @* begin
  1110.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1111.     casez (\$78 )
  1112.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" */
  1113.       1'h1:
  1114.           data_word_inv = \$80 ;
  1115.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:64" */
  1116.       default:
  1117.           data_word_inv = \$82 ;
  1118.     endcase
  1119.   end
  1120.   always @* begin
  1121.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" *)
  1122.     casez (i_blank)
  1123.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" */
  1124.       1'h1:
  1125.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:83" *)
  1126.           casez (i_c)
  1127.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:84" */
  1128.             2'h0:
  1129.                 \o_encoded$next  = 10'h354;
  1130.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:86" */
  1131.             2'h1:
  1132.                 \o_encoded$next  = 10'h0ab;
  1133.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:88" */
  1134.             2'h2:
  1135.                 \o_encoded$next  = 10'h154;
  1136.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:90" */
  1137.             default:
  1138.                 \o_encoded$next  = 10'h2ab;
  1139.           endcase
  1140.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:93" */
  1141.       default:
  1142.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1143.           casez ({ \$119 , \$105  })
  1144.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" */
  1145.             2'b?1:
  1146.                 (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" *)
  1147.                 casez (data_word[8])
  1148.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" */
  1149.                   1'h1:
  1150.                       \o_encoded$next  = \$121 ;
  1151.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:99" */
  1152.                   default:
  1153.                       \o_encoded$next  = { 2'h2, data_word_inv[7:0] };
  1154.                 endcase
  1155.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" */
  1156.             2'b1?:
  1157.                 \o_encoded$next  = { 1'h1, data_word[8], data_word_inv[7:0] };
  1158.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:106" */
  1159.             default:
  1160.                 \o_encoded$next  = { 1'h0, data_word };
  1161.           endcase
  1162.     endcase
  1163.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  1164.     casez (pixel_rst)
  1165.       1'h1:
  1166.           \o_encoded$next  = 10'h000;
  1167.     endcase
  1168.   end
  1169.   always @* begin
  1170.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" *)
  1171.     casez (i_blank)
  1172.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" */
  1173.       1'h1:
  1174.           \dc_bias$next  = 4'h0;
  1175.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:93" */
  1176.       default:
  1177.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1178.           casez ({ \$141 , \$127  })
  1179.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" */
  1180.             2'b?1:
  1181.                 (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" *)
  1182.                 casez (data_word[8])
  1183.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" */
  1184.                   1'h1:
  1185.                       \dc_bias$next  = \$143 [3:0];
  1186.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:99" */
  1187.                   default:
  1188.                       \dc_bias$next  = \$146 [3:0];
  1189.                 endcase
  1190.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" */
  1191.             2'b1?:
  1192.                 \dc_bias$next  = \$149 [3:0];
  1193.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:106" */
  1194.             default:
  1195.                 \dc_bias$next  = \$154 [3:0];
  1196.           endcase
  1197.     endcase
  1198.   end
  1199.   assign \$43  = \$58 ;
  1200.   assign \$84  = \$99 ;
  1201.   assign \$143  = \$144 ;
  1202.   assign \$146  = \$147 ;
  1203.   assign \$149  = \$152 ;
  1204.   assign \$154  = \$157 ;
  1205.   assign data_word_disparity = \$99 [3:0];
  1206.   assign ones = \$58 [3:0];
  1207.   assign xnored[8] = 1'h0;
  1208.   assign xnored[7] = \$39 ;
  1209.   assign xnored[6] = \$35 ;
  1210.   assign xnored[5] = \$31 ;
  1211.   assign xnored[4] = \$27 ;
  1212.   assign xnored[3] = \$23 ;
  1213.   assign xnored[2] = \$19 ;
  1214.   assign xnored[1] = \$15 ;
  1215.   assign xnored[0] = i_data[0];
  1216.   assign xored[8] = 1'h1;
  1217.   assign xored[7] = \$13 ;
  1218.   assign xored[6] = \$11 ;
  1219.   assign xored[5] = \$9 ;
  1220.   assign xored[4] = \$7 ;
  1221.   assign xored[3] = \$5 ;
  1222.   assign xored[2] = \$3 ;
  1223.   assign xored[1] = \$1 ;
  1224.   assign xored[0] = i_data[0];
  1225. endmodule
  1226.  
  1227. (* \nmigen.hierarchy  = "top.top.vga2dvid.u22" *)
  1228. (* generator = "nMigen" *)
  1229. module u22(pixel_clk, i_data, i_c, i_blank, o_encoded, pixel_rst);
  1230.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:25" *)
  1231.   wire \$1 ;
  1232.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1233.   wire \$101 ;
  1234.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1235.   wire \$103 ;
  1236.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1237.   wire \$105 ;
  1238.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1239.   wire \$107 ;
  1240.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1241.   wire \$109 ;
  1242.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:30" *)
  1243.   wire \$11 ;
  1244.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1245.   wire \$111 ;
  1246.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1247.   wire \$113 ;
  1248.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1249.   wire \$115 ;
  1250.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1251.   wire \$117 ;
  1252.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1253.   wire \$119 ;
  1254.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:97" *)
  1255.   wire [9:0] \$121 ;
  1256.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1257.   wire \$123 ;
  1258.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1259.   wire \$125 ;
  1260.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1261.   wire \$127 ;
  1262.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1263.   wire \$129 ;
  1264.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:31" *)
  1265.   wire \$13 ;
  1266.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1267.   wire \$131 ;
  1268.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1269.   wire \$133 ;
  1270.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1271.   wire \$135 ;
  1272.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1273.   wire \$137 ;
  1274.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1275.   wire \$139 ;
  1276.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1277.   wire \$141 ;
  1278.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:98" *)
  1279.   wire [4:0] \$143 ;
  1280.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:98" *)
  1281.   wire [4:0] \$144 ;
  1282.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:101" *)
  1283.   wire [4:0] \$146 ;
  1284.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:101" *)
  1285.   wire [4:0] \$147 ;
  1286.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *)
  1287.   wire [5:0] \$149 ;
  1288.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *)
  1289.   wire \$15 ;
  1290.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *)
  1291.   wire [4:0] \$150 ;
  1292.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *)
  1293.   wire [5:0] \$152 ;
  1294.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *)
  1295.   wire [5:0] \$154 ;
  1296.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *)
  1297.   wire [4:0] \$155 ;
  1298.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *)
  1299.   wire [5:0] \$157 ;
  1300.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *)
  1301.   wire \$16 ;
  1302.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *)
  1303.   wire \$19 ;
  1304.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *)
  1305.   wire \$20 ;
  1306.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *)
  1307.   wire \$23 ;
  1308.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *)
  1309.   wire \$24 ;
  1310.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *)
  1311.   wire \$27 ;
  1312.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *)
  1313.   wire \$28 ;
  1314.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:26" *)
  1315.   wire \$3 ;
  1316.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *)
  1317.   wire \$31 ;
  1318.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *)
  1319.   wire \$32 ;
  1320.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *)
  1321.   wire \$35 ;
  1322.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *)
  1323.   wire \$36 ;
  1324.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *)
  1325.   wire \$39 ;
  1326.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *)
  1327.   wire \$40 ;
  1328.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1329.   wire [8:0] \$43 ;
  1330.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1331.   wire [1:0] \$44 ;
  1332.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1333.   wire [2:0] \$46 ;
  1334.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1335.   wire [3:0] \$48 ;
  1336.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:27" *)
  1337.   wire \$5 ;
  1338.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1339.   wire [4:0] \$50 ;
  1340.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1341.   wire [5:0] \$52 ;
  1342.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1343.   wire [6:0] \$54 ;
  1344.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1345.   wire [7:0] \$56 ;
  1346.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1347.   wire [8:0] \$58 ;
  1348.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1349.   wire \$60 ;
  1350.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1351.   wire \$62 ;
  1352.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1353.   wire \$64 ;
  1354.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1355.   wire \$66 ;
  1356.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1357.   wire \$68 ;
  1358.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:28" *)
  1359.   wire \$7 ;
  1360.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1361.   wire \$70 ;
  1362.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1363.   wire \$72 ;
  1364.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1365.   wire \$74 ;
  1366.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1367.   wire \$76 ;
  1368.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1369.   wire \$78 ;
  1370.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:63" *)
  1371.   wire [8:0] \$80 ;
  1372.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:66" *)
  1373.   wire [8:0] \$82 ;
  1374.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1375.   wire [11:0] \$84 ;
  1376.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1377.   wire [4:0] \$85 ;
  1378.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1379.   wire [5:0] \$87 ;
  1380.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1381.   wire [6:0] \$89 ;
  1382.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:29" *)
  1383.   wire \$9 ;
  1384.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1385.   wire [7:0] \$91 ;
  1386.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1387.   wire [8:0] \$93 ;
  1388.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1389.   wire [9:0] \$95 ;
  1390.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1391.   wire [10:0] \$97 ;
  1392.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1393.   wire [11:0] \$99 ;
  1394.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:18" *)
  1395.   reg [8:0] data_word;
  1396.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:20" *)
  1397.   wire [3:0] data_word_disparity;
  1398.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:19" *)
  1399.   reg [8:0] data_word_inv;
  1400.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:21" *)
  1401.   reg [3:0] dc_bias = 4'h0;
  1402.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:21" *)
  1403.   reg [3:0] \dc_bias$next ;
  1404.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:9" *)
  1405.   input i_blank;
  1406.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:8" *)
  1407.   input [1:0] i_c;
  1408.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:7" *)
  1409.   input [7:0] i_data;
  1410.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:10" *)
  1411.   output [9:0] o_encoded;
  1412.   reg [9:0] o_encoded = 10'h000;
  1413.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:10" *)
  1414.   reg [9:0] \o_encoded$next ;
  1415.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:17" *)
  1416.   wire [3:0] ones;
  1417.   (* src = "top_vgatest.py:101" *)
  1418.   input pixel_clk;
  1419.   (* src = "top_vgatest.py:101" *)
  1420.   input pixel_rst;
  1421.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:16" *)
  1422.   wire [8:0] xnored;
  1423.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:15" *)
  1424.   wire [8:0] xored;
  1425.   assign \$9  = i_data[5] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:29" *) xored[4];
  1426.   assign \$99  = \$97  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[7];
  1427.   assign \$101  = dc_bias == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  1428.   assign \$103  = data_word_disparity == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  1429.   assign \$105  = \$101  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) \$103 ;
  1430.   assign \$107  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  1431.   assign \$109  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  1432.   assign \$111  = \$107  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$109 ;
  1433.   assign \$113  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  1434.   assign \$115  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  1435.   assign \$117  = \$113  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) \$115 ;
  1436.   assign \$11  = i_data[6] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:30" *) xored[5];
  1437.   assign \$119  = \$111  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$117 ;
  1438.   assign \$121  = + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:97" *) { 1'h1, data_word[7:0] };
  1439.   assign \$123  = dc_bias == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  1440.   assign \$125  = data_word_disparity == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  1441.   assign \$127  = \$123  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) \$125 ;
  1442.   assign \$129  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  1443.   assign \$131  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  1444.   assign \$133  = \$129  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$131 ;
  1445.   assign \$135  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  1446.   assign \$137  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  1447.   assign \$13  = i_data[7] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:31" *) xored[6];
  1448.   assign \$139  = \$135  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) \$137 ;
  1449.   assign \$141  = \$133  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$139 ;
  1450.   assign \$144  = dc_bias + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:98" *) data_word_disparity;
  1451.   assign \$147  = dc_bias - (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:101" *) data_word_disparity;
  1452.   assign \$150  = dc_bias + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *) data_word[8];
  1453.   assign \$152  = \$150  - (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *) data_word_disparity;
  1454.   assign \$155  = dc_bias - (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *) data_word_inv[8];
  1455.   assign \$157  = \$155  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *) data_word_disparity;
  1456.   assign \$16  = i_data[1] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *) xnored[0];
  1457.   assign \$15  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *) \$16 ;
  1458.   assign \$1  = i_data[1] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:25" *) xored[0];
  1459.   assign \$20  = i_data[2] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *) xnored[1];
  1460.   assign \$19  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *) \$20 ;
  1461.   assign \$24  = i_data[3] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *) xnored[2];
  1462.   assign \$23  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *) \$24 ;
  1463.   assign \$28  = i_data[4] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *) xnored[3];
  1464.   assign \$27  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *) \$28 ;
  1465.   assign \$32  = i_data[5] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *) xnored[4];
  1466.   assign \$31  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *) \$32 ;
  1467.   assign \$36  = i_data[6] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *) xnored[5];
  1468.   assign \$35  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *) \$36 ;
  1469.   assign \$3  = i_data[2] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:26" *) xored[1];
  1470.   assign \$40  = i_data[7] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *) xnored[6];
  1471.   assign \$39  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *) \$40 ;
  1472.   assign \$44  = 1'h0 + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[0];
  1473.   assign \$46  = \$44  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[1];
  1474.   assign \$48  = \$46  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[2];
  1475.   assign \$50  = \$48  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[3];
  1476.   assign \$52  = \$50  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[4];
  1477.   assign \$54  = \$52  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[5];
  1478.   assign \$56  = \$54  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[6];
  1479.   assign \$58  = \$56  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[7];
  1480.   assign \$5  = i_data[3] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:27" *) xored[2];
  1481.   assign \$60  = ones > (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  1482.   assign \$62  = ones == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  1483.   assign \$64  = i_data[0] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 1'h0;
  1484.   assign \$66  = \$62  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$64 ;
  1485.   assign \$68  = \$60  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$66 ;
  1486.   assign \$70  = ones > (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  1487.   assign \$72  = ones == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  1488.   assign \$74  = i_data[0] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 1'h0;
  1489.   assign \$76  = \$72  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$74 ;
  1490.   assign \$78  = \$70  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$76 ;
  1491.   assign \$7  = i_data[4] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:28" *) xored[3];
  1492.   assign \$80  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:63" *) xnored;
  1493.   assign \$82  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:66" *) xored;
  1494.   assign \$85  = 4'hc + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[0];
  1495.   assign \$87  = \$85  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[1];
  1496.   assign \$89  = \$87  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[2];
  1497.   assign \$91  = \$89  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[3];
  1498.   assign \$93  = \$91  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[4];
  1499.   assign \$95  = \$93  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[5];
  1500.   assign \$97  = \$95  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[6];
  1501.   always @(posedge pixel_clk)
  1502.       dc_bias <= \dc_bias$next ;
  1503.   always @(posedge pixel_clk)
  1504.       o_encoded <= \o_encoded$next ;
  1505.   always @* begin
  1506.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1507.     casez (\$68 )
  1508.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" */
  1509.       1'h1:
  1510.           data_word = xnored;
  1511.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:64" */
  1512.       default:
  1513.           data_word = xored;
  1514.     endcase
  1515.   end
  1516.   always @* begin
  1517.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1518.     casez (\$78 )
  1519.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" */
  1520.       1'h1:
  1521.           data_word_inv = \$80 ;
  1522.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:64" */
  1523.       default:
  1524.           data_word_inv = \$82 ;
  1525.     endcase
  1526.   end
  1527.   always @* begin
  1528.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" *)
  1529.     casez (i_blank)
  1530.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" */
  1531.       1'h1:
  1532.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:83" *)
  1533.           casez (i_c)
  1534.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:84" */
  1535.             2'h0:
  1536.                 \o_encoded$next  = 10'h354;
  1537.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:86" */
  1538.             2'h1:
  1539.                 \o_encoded$next  = 10'h0ab;
  1540.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:88" */
  1541.             2'h2:
  1542.                 \o_encoded$next  = 10'h154;
  1543.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:90" */
  1544.             default:
  1545.                 \o_encoded$next  = 10'h2ab;
  1546.           endcase
  1547.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:93" */
  1548.       default:
  1549.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1550.           casez ({ \$119 , \$105  })
  1551.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" */
  1552.             2'b?1:
  1553.                 (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" *)
  1554.                 casez (data_word[8])
  1555.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" */
  1556.                   1'h1:
  1557.                       \o_encoded$next  = \$121 ;
  1558.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:99" */
  1559.                   default:
  1560.                       \o_encoded$next  = { 2'h2, data_word_inv[7:0] };
  1561.                 endcase
  1562.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" */
  1563.             2'b1?:
  1564.                 \o_encoded$next  = { 1'h1, data_word[8], data_word_inv[7:0] };
  1565.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:106" */
  1566.             default:
  1567.                 \o_encoded$next  = { 1'h0, data_word };
  1568.           endcase
  1569.     endcase
  1570.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  1571.     casez (pixel_rst)
  1572.       1'h1:
  1573.           \o_encoded$next  = 10'h000;
  1574.     endcase
  1575.   end
  1576.   always @* begin
  1577.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" *)
  1578.     casez (i_blank)
  1579.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" */
  1580.       1'h1:
  1581.           \dc_bias$next  = 4'h0;
  1582.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:93" */
  1583.       default:
  1584.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1585.           casez ({ \$141 , \$127  })
  1586.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" */
  1587.             2'b?1:
  1588.                 (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" *)
  1589.                 casez (data_word[8])
  1590.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" */
  1591.                   1'h1:
  1592.                       \dc_bias$next  = \$143 [3:0];
  1593.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:99" */
  1594.                   default:
  1595.                       \dc_bias$next  = \$146 [3:0];
  1596.                 endcase
  1597.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" */
  1598.             2'b1?:
  1599.                 \dc_bias$next  = \$149 [3:0];
  1600.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:106" */
  1601.             default:
  1602.                 \dc_bias$next  = \$154 [3:0];
  1603.           endcase
  1604.     endcase
  1605.   end
  1606.   assign \$43  = \$58 ;
  1607.   assign \$84  = \$99 ;
  1608.   assign \$143  = \$144 ;
  1609.   assign \$146  = \$147 ;
  1610.   assign \$149  = \$152 ;
  1611.   assign \$154  = \$157 ;
  1612.   assign data_word_disparity = \$99 [3:0];
  1613.   assign ones = \$58 [3:0];
  1614.   assign xnored[8] = 1'h0;
  1615.   assign xnored[7] = \$39 ;
  1616.   assign xnored[6] = \$35 ;
  1617.   assign xnored[5] = \$31 ;
  1618.   assign xnored[4] = \$27 ;
  1619.   assign xnored[3] = \$23 ;
  1620.   assign xnored[2] = \$19 ;
  1621.   assign xnored[1] = \$15 ;
  1622.   assign xnored[0] = i_data[0];
  1623.   assign xored[8] = 1'h1;
  1624.   assign xored[7] = \$13 ;
  1625.   assign xored[6] = \$11 ;
  1626.   assign xored[5] = \$9 ;
  1627.   assign xored[4] = \$7 ;
  1628.   assign xored[3] = \$5 ;
  1629.   assign xored[2] = \$3 ;
  1630.   assign xored[1] = \$1 ;
  1631.   assign xored[0] = i_data[0];
  1632. endmodule
  1633.  
  1634. (* \nmigen.hierarchy  = "top.top.vga2dvid.u23" *)
  1635. (* generator = "nMigen" *)
  1636. module u23(pixel_clk, i_data, i_c, i_blank, o_encoded, pixel_rst);
  1637.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:25" *)
  1638.   wire \$1 ;
  1639.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1640.   wire \$101 ;
  1641.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1642.   wire \$103 ;
  1643.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1644.   wire \$105 ;
  1645.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1646.   wire \$107 ;
  1647.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1648.   wire \$109 ;
  1649.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:30" *)
  1650.   wire \$11 ;
  1651.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1652.   wire \$111 ;
  1653.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1654.   wire \$113 ;
  1655.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1656.   wire \$115 ;
  1657.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1658.   wire \$117 ;
  1659.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1660.   wire \$119 ;
  1661.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:97" *)
  1662.   wire [9:0] \$121 ;
  1663.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1664.   wire \$123 ;
  1665.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1666.   wire \$125 ;
  1667.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1668.   wire \$127 ;
  1669.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1670.   wire \$129 ;
  1671.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:31" *)
  1672.   wire \$13 ;
  1673.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1674.   wire \$131 ;
  1675.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1676.   wire \$133 ;
  1677.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1678.   wire \$135 ;
  1679.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1680.   wire \$137 ;
  1681.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1682.   wire \$139 ;
  1683.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1684.   wire \$141 ;
  1685.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:98" *)
  1686.   wire [4:0] \$143 ;
  1687.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:98" *)
  1688.   wire [4:0] \$144 ;
  1689.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:101" *)
  1690.   wire [4:0] \$146 ;
  1691.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:101" *)
  1692.   wire [4:0] \$147 ;
  1693.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *)
  1694.   wire [5:0] \$149 ;
  1695.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *)
  1696.   wire \$15 ;
  1697.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *)
  1698.   wire [4:0] \$150 ;
  1699.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *)
  1700.   wire [5:0] \$152 ;
  1701.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *)
  1702.   wire [5:0] \$154 ;
  1703.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *)
  1704.   wire [4:0] \$155 ;
  1705.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *)
  1706.   wire [5:0] \$157 ;
  1707.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *)
  1708.   wire \$16 ;
  1709.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *)
  1710.   wire \$19 ;
  1711.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *)
  1712.   wire \$20 ;
  1713.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *)
  1714.   wire \$23 ;
  1715.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *)
  1716.   wire \$24 ;
  1717.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *)
  1718.   wire \$27 ;
  1719.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *)
  1720.   wire \$28 ;
  1721.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:26" *)
  1722.   wire \$3 ;
  1723.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *)
  1724.   wire \$31 ;
  1725.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *)
  1726.   wire \$32 ;
  1727.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *)
  1728.   wire \$35 ;
  1729.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *)
  1730.   wire \$36 ;
  1731.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *)
  1732.   wire \$39 ;
  1733.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *)
  1734.   wire \$40 ;
  1735.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1736.   wire [8:0] \$43 ;
  1737.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1738.   wire [1:0] \$44 ;
  1739.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1740.   wire [2:0] \$46 ;
  1741.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1742.   wire [3:0] \$48 ;
  1743.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:27" *)
  1744.   wire \$5 ;
  1745.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1746.   wire [4:0] \$50 ;
  1747.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1748.   wire [5:0] \$52 ;
  1749.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1750.   wire [6:0] \$54 ;
  1751.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1752.   wire [7:0] \$56 ;
  1753.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1754.   wire [8:0] \$58 ;
  1755.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1756.   wire \$60 ;
  1757.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1758.   wire \$62 ;
  1759.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1760.   wire \$64 ;
  1761.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1762.   wire \$66 ;
  1763.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1764.   wire \$68 ;
  1765.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:28" *)
  1766.   wire \$7 ;
  1767.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1768.   wire \$70 ;
  1769.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1770.   wire \$72 ;
  1771.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1772.   wire \$74 ;
  1773.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1774.   wire \$76 ;
  1775.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1776.   wire \$78 ;
  1777.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:63" *)
  1778.   wire [8:0] \$80 ;
  1779.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:66" *)
  1780.   wire [8:0] \$82 ;
  1781.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1782.   wire [11:0] \$84 ;
  1783.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1784.   wire [4:0] \$85 ;
  1785.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1786.   wire [5:0] \$87 ;
  1787.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1788.   wire [6:0] \$89 ;
  1789.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:29" *)
  1790.   wire \$9 ;
  1791.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1792.   wire [7:0] \$91 ;
  1793.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1794.   wire [8:0] \$93 ;
  1795.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1796.   wire [9:0] \$95 ;
  1797.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1798.   wire [10:0] \$97 ;
  1799.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1800.   wire [11:0] \$99 ;
  1801.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:18" *)
  1802.   reg [8:0] data_word;
  1803.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:20" *)
  1804.   wire [3:0] data_word_disparity;
  1805.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:19" *)
  1806.   reg [8:0] data_word_inv;
  1807.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:21" *)
  1808.   reg [3:0] dc_bias = 4'h0;
  1809.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:21" *)
  1810.   reg [3:0] \dc_bias$next ;
  1811.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:9" *)
  1812.   input i_blank;
  1813.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:8" *)
  1814.   input [1:0] i_c;
  1815.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:7" *)
  1816.   input [7:0] i_data;
  1817.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:10" *)
  1818.   output [9:0] o_encoded;
  1819.   reg [9:0] o_encoded = 10'h000;
  1820.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:10" *)
  1821.   reg [9:0] \o_encoded$next ;
  1822.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:17" *)
  1823.   wire [3:0] ones;
  1824.   (* src = "top_vgatest.py:101" *)
  1825.   input pixel_clk;
  1826.   (* src = "top_vgatest.py:101" *)
  1827.   input pixel_rst;
  1828.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:16" *)
  1829.   wire [8:0] xnored;
  1830.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:15" *)
  1831.   wire [8:0] xored;
  1832.   assign \$9  = i_data[5] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:29" *) xored[4];
  1833.   assign \$99  = \$97  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[7];
  1834.   assign \$101  = dc_bias == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  1835.   assign \$103  = data_word_disparity == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  1836.   assign \$105  = \$101  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) \$103 ;
  1837.   assign \$107  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  1838.   assign \$109  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  1839.   assign \$111  = \$107  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$109 ;
  1840.   assign \$113  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  1841.   assign \$115  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  1842.   assign \$117  = \$113  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) \$115 ;
  1843.   assign \$11  = i_data[6] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:30" *) xored[5];
  1844.   assign \$119  = \$111  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$117 ;
  1845.   assign \$121  = + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:97" *) { 1'h1, data_word[7:0] };
  1846.   assign \$123  = dc_bias == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  1847.   assign \$125  = data_word_disparity == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  1848.   assign \$127  = \$123  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) \$125 ;
  1849.   assign \$129  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  1850.   assign \$131  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  1851.   assign \$133  = \$129  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$131 ;
  1852.   assign \$135  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  1853.   assign \$137  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  1854.   assign \$13  = i_data[7] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:31" *) xored[6];
  1855.   assign \$139  = \$135  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) \$137 ;
  1856.   assign \$141  = \$133  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$139 ;
  1857.   assign \$144  = dc_bias + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:98" *) data_word_disparity;
  1858.   assign \$147  = dc_bias - (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:101" *) data_word_disparity;
  1859.   assign \$150  = dc_bias + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *) data_word[8];
  1860.   assign \$152  = \$150  - (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *) data_word_disparity;
  1861.   assign \$155  = dc_bias - (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *) data_word_inv[8];
  1862.   assign \$157  = \$155  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *) data_word_disparity;
  1863.   assign \$16  = i_data[1] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *) xnored[0];
  1864.   assign \$15  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *) \$16 ;
  1865.   assign \$1  = i_data[1] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:25" *) xored[0];
  1866.   assign \$20  = i_data[2] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *) xnored[1];
  1867.   assign \$19  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *) \$20 ;
  1868.   assign \$24  = i_data[3] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *) xnored[2];
  1869.   assign \$23  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *) \$24 ;
  1870.   assign \$28  = i_data[4] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *) xnored[3];
  1871.   assign \$27  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *) \$28 ;
  1872.   assign \$32  = i_data[5] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *) xnored[4];
  1873.   assign \$31  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *) \$32 ;
  1874.   assign \$36  = i_data[6] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *) xnored[5];
  1875.   assign \$35  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *) \$36 ;
  1876.   assign \$3  = i_data[2] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:26" *) xored[1];
  1877.   assign \$40  = i_data[7] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *) xnored[6];
  1878.   assign \$39  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *) \$40 ;
  1879.   assign \$44  = 1'h0 + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[0];
  1880.   assign \$46  = \$44  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[1];
  1881.   assign \$48  = \$46  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[2];
  1882.   assign \$50  = \$48  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[3];
  1883.   assign \$52  = \$50  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[4];
  1884.   assign \$54  = \$52  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[5];
  1885.   assign \$56  = \$54  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[6];
  1886.   assign \$58  = \$56  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[7];
  1887.   assign \$5  = i_data[3] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:27" *) xored[2];
  1888.   assign \$60  = ones > (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  1889.   assign \$62  = ones == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  1890.   assign \$64  = i_data[0] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 1'h0;
  1891.   assign \$66  = \$62  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$64 ;
  1892.   assign \$68  = \$60  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$66 ;
  1893.   assign \$70  = ones > (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  1894.   assign \$72  = ones == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  1895.   assign \$74  = i_data[0] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 1'h0;
  1896.   assign \$76  = \$72  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$74 ;
  1897.   assign \$78  = \$70  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$76 ;
  1898.   assign \$7  = i_data[4] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:28" *) xored[3];
  1899.   assign \$80  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:63" *) xnored;
  1900.   assign \$82  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:66" *) xored;
  1901.   assign \$85  = 4'hc + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[0];
  1902.   assign \$87  = \$85  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[1];
  1903.   assign \$89  = \$87  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[2];
  1904.   assign \$91  = \$89  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[3];
  1905.   assign \$93  = \$91  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[4];
  1906.   assign \$95  = \$93  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[5];
  1907.   assign \$97  = \$95  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[6];
  1908.   always @(posedge pixel_clk)
  1909.       dc_bias <= \dc_bias$next ;
  1910.   always @(posedge pixel_clk)
  1911.       o_encoded <= \o_encoded$next ;
  1912.   always @* begin
  1913.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1914.     casez (\$68 )
  1915.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" */
  1916.       1'h1:
  1917.           data_word = xnored;
  1918.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:64" */
  1919.       default:
  1920.           data_word = xored;
  1921.     endcase
  1922.   end
  1923.   always @* begin
  1924.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1925.     casez (\$78 )
  1926.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" */
  1927.       1'h1:
  1928.           data_word_inv = \$80 ;
  1929.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:64" */
  1930.       default:
  1931.           data_word_inv = \$82 ;
  1932.     endcase
  1933.   end
  1934.   always @* begin
  1935.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" *)
  1936.     casez (i_blank)
  1937.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" */
  1938.       1'h1:
  1939.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:83" *)
  1940.           casez (i_c)
  1941.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:84" */
  1942.             2'h0:
  1943.                 \o_encoded$next  = 10'h354;
  1944.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:86" */
  1945.             2'h1:
  1946.                 \o_encoded$next  = 10'h0ab;
  1947.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:88" */
  1948.             2'h2:
  1949.                 \o_encoded$next  = 10'h154;
  1950.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:90" */
  1951.             default:
  1952.                 \o_encoded$next  = 10'h2ab;
  1953.           endcase
  1954.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:93" */
  1955.       default:
  1956.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1957.           casez ({ \$119 , \$105  })
  1958.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" */
  1959.             2'b?1:
  1960.                 (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" *)
  1961.                 casez (data_word[8])
  1962.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" */
  1963.                   1'h1:
  1964.                       \o_encoded$next  = \$121 ;
  1965.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:99" */
  1966.                   default:
  1967.                       \o_encoded$next  = { 2'h2, data_word_inv[7:0] };
  1968.                 endcase
  1969.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" */
  1970.             2'b1?:
  1971.                 \o_encoded$next  = { 1'h1, data_word[8], data_word_inv[7:0] };
  1972.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:106" */
  1973.             default:
  1974.                 \o_encoded$next  = { 1'h0, data_word };
  1975.           endcase
  1976.     endcase
  1977.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  1978.     casez (pixel_rst)
  1979.       1'h1:
  1980.           \o_encoded$next  = 10'h000;
  1981.     endcase
  1982.   end
  1983.   always @* begin
  1984.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" *)
  1985.     casez (i_blank)
  1986.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" */
  1987.       1'h1:
  1988.           \dc_bias$next  = 4'h0;
  1989.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:93" */
  1990.       default:
  1991.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1992.           casez ({ \$141 , \$127  })
  1993.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" */
  1994.             2'b?1:
  1995.                 (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" *)
  1996.                 casez (data_word[8])
  1997.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" */
  1998.                   1'h1:
  1999.                       \dc_bias$next  = \$143 [3:0];
  2000.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:99" */
  2001.                   default:
  2002.                       \dc_bias$next  = \$146 [3:0];
  2003.                 endcase
  2004.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" */
  2005.             2'b1?:
  2006.                 \dc_bias$next  = \$149 [3:0];
  2007.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:106" */
  2008.             default:
  2009.                 \dc_bias$next  = \$154 [3:0];
  2010.           endcase
  2011.     endcase
  2012.   end
  2013.   assign \$43  = \$58 ;
  2014.   assign \$84  = \$99 ;
  2015.   assign \$143  = \$144 ;
  2016.   assign \$146  = \$147 ;
  2017.   assign \$149  = \$152 ;
  2018.   assign \$154  = \$157 ;
  2019.   assign data_word_disparity = \$99 [3:0];
  2020.   assign ones = \$58 [3:0];
  2021.   assign xnored[8] = 1'h0;
  2022.   assign xnored[7] = \$39 ;
  2023.   assign xnored[6] = \$35 ;
  2024.   assign xnored[5] = \$31 ;
  2025.   assign xnored[4] = \$27 ;
  2026.   assign xnored[3] = \$23 ;
  2027.   assign xnored[2] = \$19 ;
  2028.   assign xnored[1] = \$15 ;
  2029.   assign xnored[0] = i_data[0];
  2030.   assign xored[8] = 1'h1;
  2031.   assign xored[7] = \$13 ;
  2032.   assign xored[6] = \$11 ;
  2033.   assign xored[5] = \$9 ;
  2034.   assign xored[4] = \$7 ;
  2035.   assign xored[3] = \$5 ;
  2036.   assign xored[2] = \$3 ;
  2037.   assign xored[1] = \$1 ;
  2038.   assign xored[0] = i_data[0];
  2039. endmodule
  2040.  
  2041. (* \nmigen.hierarchy  = "top.top.vga" *)
  2042. (* generator = "nMigen" *)
  2043. module vga(o_vga_r, o_vga_g, o_vga_b, o_vga_hsync, o_vga_vsync, o_vga_blank, pixel_rst, pixel_clk, i_clk_en);
  2044.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:98" *)
  2045.   wire \$1 ;
  2046.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:104" *)
  2047.   wire [16:0] \$10 ;
  2048.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:104" *)
  2049.   wire [16:0] \$11 ;
  2050.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:119" *)
  2051.   wire \$13 ;
  2052.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:124" *)
  2053.   wire \$15 ;
  2054.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:119" *)
  2055.   wire \$17 ;
  2056.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:124" *)
  2057.   wire \$19 ;
  2058.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:129" *)
  2059.   wire \$21 ;
  2060.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:131" *)
  2061.   wire \$23 ;
  2062.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:134" *)
  2063.   wire \$25 ;
  2064.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:139" *)
  2065.   wire \$27 ;
  2066.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:134" *)
  2067.   wire \$29 ;
  2068.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:106" *)
  2069.   wire [16:0] \$3 ;
  2070.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:139" *)
  2071.   wire \$31 ;
  2072.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:144" *)
  2073.   wire \$33 ;
  2074.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:146" *)
  2075.   wire \$35 ;
  2076.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:152" *)
  2077.   wire [7:0] \$37 ;
  2078.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:153" *)
  2079.   wire \$38 ;
  2080.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:106" *)
  2081.   wire [16:0] \$4 ;
  2082.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:153" *)
  2083.   wire \$40 ;
  2084.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:153" *)
  2085.   wire \$42 ;
  2086.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:155" *)
  2087.   wire [7:0] \$45 ;
  2088.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:156" *)
  2089.   wire \$46 ;
  2090.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:158" *)
  2091.   wire [7:0] \$49 ;
  2092.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:158" *)
  2093.   wire [7:0] \$50 ;
  2094.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:159" *)
  2095.   wire [1:0] \$51 ;
  2096.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:159" *)
  2097.   wire \$53 ;
  2098.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:172" *)
  2099.   wire [5:0] \$56 ;
  2100.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:172" *)
  2101.   wire [7:0] \$58 ;
  2102.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:98" *)
  2103.   wire \$6 ;
  2104.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:172" *)
  2105.   wire [7:0] \$60 ;
  2106.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:172" *)
  2107.   wire [7:0] \$62 ;
  2108.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:173" *)
  2109.   wire [7:0] \$64 ;
  2110.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:173" *)
  2111.   wire [7:0] \$66 ;
  2112.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:173" *)
  2113.   wire [7:0] \$68 ;
  2114.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:173" *)
  2115.   wire [7:0] \$70 ;
  2116.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:174" *)
  2117.   wire [7:0] \$72 ;
  2118.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:174" *)
  2119.   wire [7:0] \$74 ;
  2120.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:101" *)
  2121.   wire \$8 ;
  2122.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:93" *)
  2123.   wire [7:0] A;
  2124.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:77" *)
  2125.   reg [15:0] CounterX = 16'h0000;
  2126.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:77" *)
  2127.   reg [15:0] \CounterX$next ;
  2128.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:78" *)
  2129.   reg [15:0] CounterY = 16'h0000;
  2130.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:78" *)
  2131.   reg [15:0] \CounterY$next ;
  2132.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:81" *)
  2133.   reg R_blank = 1'h0;
  2134.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:81" *)
  2135.   reg \R_blank$next ;
  2136.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:85" *)
  2137.   reg R_blank_early = 1'h0;
  2138.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:85" *)
  2139.   reg \R_blank_early$next ;
  2140.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:82" *)
  2141.   reg R_disp = 1'h0;
  2142.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:82" *)
  2143.   reg \R_disp$next ;
  2144.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:83" *)
  2145.   reg R_disp_early = 1'h0;
  2146.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:83" *)
  2147.   reg \R_disp_early$next ;
  2148.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:87" *)
  2149.   reg R_fetch_next = 1'h0;
  2150.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:87" *)
  2151.   reg \R_fetch_next$next ;
  2152.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:79" *)
  2153.   reg R_hsync = 1'h0;
  2154.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:79" *)
  2155.   reg \R_hsync$next ;
  2156.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:86" *)
  2157.   reg R_vblank = 1'h0;
  2158.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:86" *)
  2159.   reg \R_vblank$next ;
  2160.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:84" *)
  2161.   reg R_vdisp = 1'h0;
  2162.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:84" *)
  2163.   reg \R_vdisp$next ;
  2164.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:90" *)
  2165.   reg [7:0] R_vga_b = 8'h00;
  2166.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:90" *)
  2167.   reg [7:0] \R_vga_b$next ;
  2168.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:89" *)
  2169.   reg [7:0] R_vga_g = 8'h00;
  2170.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:89" *)
  2171.   reg [7:0] \R_vga_g$next ;
  2172.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:88" *)
  2173.   reg [7:0] R_vga_r = 8'h00;
  2174.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:88" *)
  2175.   reg [7:0] \R_vga_r$next ;
  2176.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:80" *)
  2177.   reg R_vsync = 1'h0;
  2178.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:80" *)
  2179.   reg \R_vsync$next ;
  2180.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:94" *)
  2181.   wire [7:0] T;
  2182.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:92" *)
  2183.   wire [7:0] W;
  2184.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:95" *)
  2185.   wire [5:0] Z;
  2186.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:29" *)
  2187.   input i_clk_en;
  2188.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:35" *)
  2189.   wire [15:0] o_beam_x;
  2190.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:36" *)
  2191.   wire [15:0] o_beam_y;
  2192.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:34" *)
  2193.   wire o_fetch_next;
  2194.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:39" *)
  2195.   output [7:0] o_vga_b;
  2196.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:43" *)
  2197.   output o_vga_blank;
  2198.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:44" *)
  2199.   wire o_vga_de;
  2200.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:38" *)
  2201.   output [7:0] o_vga_g;
  2202.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:40" *)
  2203.   output o_vga_hsync;
  2204.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:37" *)
  2205.   output [7:0] o_vga_r;
  2206.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:41" *)
  2207.   output o_vga_vsync;
  2208.   (* src = "top_vgatest.py:101" *)
  2209.   input pixel_clk;
  2210.   (* src = "top_vgatest.py:101" *)
  2211.   input pixel_rst;
  2212.   assign \$11  = CounterY + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:104" *) 1'h1;
  2213.   assign \$13  = CounterX == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:119" *) 16'h04ff;
  2214.   assign \$15  = CounterX == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:124" *) 16'h059f;
  2215.   assign \$17  = CounterX == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:119" *) 16'h04ff;
  2216.   assign \$1  = CounterX == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:98" *) 16'h059f;
  2217.   assign \$19  = CounterX == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:124" *) 16'h059f;
  2218.   assign \$21  = CounterX == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:129" *) 16'h052f;
  2219.   assign \$23  = CounterX == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:131" *) 16'h054f;
  2220.   assign \$25  = CounterY == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:134" *) 16'h031f;
  2221.   assign \$27  = CounterY == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:139" *) 16'h0336;
  2222.   assign \$29  = CounterY == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:134" *) 16'h031f;
  2223.   assign \$31  = CounterY == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:139" *) 16'h0336;
  2224.   assign \$33  = CounterY == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:144" *) 16'h0322;
  2225.   assign \$35  = CounterY == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:146" *) 16'h0328;
  2226.   assign \$38  = CounterX[7:5] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:153" *) 2'h2;
  2227.   assign \$40  = CounterY[7:5] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:153" *) 2'h2;
  2228.   assign \$42  = \$38  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:153" *) \$40 ;
  2229.   assign \$37  = \$42  ? (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:152" *) 8'hff : 8'h00;
  2230.   assign \$46  = CounterX[7:0] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:156" *) CounterY[7:0];
  2231.   assign \$45  = \$46  ? (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:155" *) 8'hff : 8'h00;
  2232.   assign \$4  = CounterX + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:106" *) 1'h1;
  2233.   assign \$51  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:159" *) CounterX[4:3];
  2234.   assign \$53  = CounterY[4:3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:159" *) \$51 ;
  2235.   assign \$50  = \$53  ? (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:158" *) 8'hff : 8'h00;
  2236.   assign \$56  = CounterX[5:0] & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:172" *) Z;
  2237.   assign \$58  = { \$56 , 1'h0 } | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:172" *) W;
  2238.   assign \$60  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:172" *) A;
  2239.   assign \$62  = \$58  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:172" *) \$60 ;
  2240.   assign \$64  = CounterX[7:0] & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:173" *) T;
  2241.   assign \$66  = \$64  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:173" *) W;
  2242.   assign \$68  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:173" *) A;
  2243.   assign \$6  = CounterX == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:98" *) 16'h059f;
  2244.   assign \$70  = \$66  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:173" *) \$68 ;
  2245.   assign \$72  = CounterY[7:0] | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:174" *) W;
  2246.   assign \$74  = \$72  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:174" *) A;
  2247.   assign \$8  = CounterY == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:101" *) 16'h0336;
  2248.   always @(posedge pixel_clk)
  2249.       R_disp <= \R_disp$next ;
  2250.   always @(posedge pixel_clk)
  2251.       R_blank <= \R_blank$next ;
  2252.   always @(posedge pixel_clk)
  2253.       R_vga_b <= \R_vga_b$next ;
  2254.   always @(posedge pixel_clk)
  2255.       R_vga_g <= \R_vga_g$next ;
  2256.   always @(posedge pixel_clk)
  2257.       R_vga_r <= \R_vga_r$next ;
  2258.   always @(posedge pixel_clk)
  2259.       R_vsync <= \R_vsync$next ;
  2260.   always @(posedge pixel_clk)
  2261.       R_vdisp <= \R_vdisp$next ;
  2262.   always @(posedge pixel_clk)
  2263.       R_vblank <= \R_vblank$next ;
  2264.   always @(posedge pixel_clk)
  2265.       R_hsync <= \R_hsync$next ;
  2266.   always @(posedge pixel_clk)
  2267.       R_disp_early <= \R_disp_early$next ;
  2268.   always @(posedge pixel_clk)
  2269.       R_blank_early <= \R_blank_early$next ;
  2270.   always @(posedge pixel_clk)
  2271.       R_fetch_next <= \R_fetch_next$next ;
  2272.   always @(posedge pixel_clk)
  2273.       CounterY <= \CounterY$next ;
  2274.   always @(posedge pixel_clk)
  2275.       CounterX <= \CounterX$next ;
  2276.   always @* begin
  2277.     \CounterX$next  = CounterX;
  2278.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:97" *)
  2279.     casez (i_clk_en)
  2280.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:97" */
  2281.       1'h1:
  2282.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:98" *)
  2283.           casez (\$1 )
  2284.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:98" */
  2285.             1'h1:
  2286.                 \CounterX$next  = 16'h0000;
  2287.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:105" */
  2288.             default:
  2289.                 \CounterX$next  = \$3 [15:0];
  2290.           endcase
  2291.     endcase
  2292.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2293.     casez (pixel_rst)
  2294.       1'h1:
  2295.           \CounterX$next  = 16'h0000;
  2296.     endcase
  2297.   end
  2298.   always @* begin
  2299.     \CounterY$next  = CounterY;
  2300.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:97" *)
  2301.     casez (i_clk_en)
  2302.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:97" */
  2303.       1'h1:
  2304.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:98" *)
  2305.           casez (\$6 )
  2306.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:98" */
  2307.             1'h1:
  2308.                 (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:101" *)
  2309.                 casez (\$8 )
  2310.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:101" */
  2311.                   1'h1:
  2312.                       \CounterY$next  = 16'h0000;
  2313.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:103" */
  2314.                   default:
  2315.                       \CounterY$next  = \$10 [15:0];
  2316.                 endcase
  2317.           endcase
  2318.     endcase
  2319.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2320.     casez (pixel_rst)
  2321.       1'h1:
  2322.           \CounterY$next  = 16'h0000;
  2323.     endcase
  2324.   end
  2325.   always @* begin
  2326.     \R_vdisp$next  = R_vdisp;
  2327.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:134" *)
  2328.     casez ({ \$31 , \$29  })
  2329.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:134" */
  2330.       2'b?1:
  2331.           \R_vdisp$next  = 1'h0;
  2332.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:139" */
  2333.       2'b1?:
  2334.           \R_vdisp$next  = 1'h1;
  2335.     endcase
  2336.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2337.     casez (pixel_rst)
  2338.       1'h1:
  2339.           \R_vdisp$next  = 1'h0;
  2340.     endcase
  2341.   end
  2342.   always @* begin
  2343.     \R_vsync$next  = R_vsync;
  2344.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:144" *)
  2345.     casez ({ \$35 , \$33  })
  2346.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:144" */
  2347.       2'b?1:
  2348.           \R_vsync$next  = 1'h1;
  2349.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:146" */
  2350.       2'b1?:
  2351.           \R_vsync$next  = 1'h0;
  2352.     endcase
  2353.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2354.     casez (pixel_rst)
  2355.       1'h1:
  2356.           \R_vsync$next  = 1'h0;
  2357.     endcase
  2358.   end
  2359.   always @* begin
  2360.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:164" *)
  2361.     casez (R_blank)
  2362.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:164" */
  2363.       1'h1:
  2364.           \R_vga_r$next  = 8'h00;
  2365.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:170" */
  2366.       default:
  2367.           \R_vga_r$next  = \$62 ;
  2368.     endcase
  2369.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2370.     casez (pixel_rst)
  2371.       1'h1:
  2372.           \R_vga_r$next  = 8'h00;
  2373.     endcase
  2374.   end
  2375.   always @* begin
  2376.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:164" *)
  2377.     casez (R_blank)
  2378.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:164" */
  2379.       1'h1:
  2380.           \R_vga_g$next  = 8'h00;
  2381.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:170" */
  2382.       default:
  2383.           \R_vga_g$next  = \$70 ;
  2384.     endcase
  2385.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2386.     casez (pixel_rst)
  2387.       1'h1:
  2388.           \R_vga_g$next  = 8'h00;
  2389.     endcase
  2390.   end
  2391.   always @* begin
  2392.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:164" *)
  2393.     casez (R_blank)
  2394.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:164" */
  2395.       1'h1:
  2396.           \R_vga_b$next  = 8'h00;
  2397.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:170" */
  2398.       default:
  2399.           \R_vga_b$next  = \$74 ;
  2400.     endcase
  2401.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2402.     casez (pixel_rst)
  2403.       1'h1:
  2404.           \R_vga_b$next  = 8'h00;
  2405.     endcase
  2406.   end
  2407.   always @* begin
  2408.     \R_blank$next  = R_blank_early;
  2409.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2410.     casez (pixel_rst)
  2411.       1'h1:
  2412.           \R_blank$next  = 1'h0;
  2413.     endcase
  2414.   end
  2415.   always @* begin
  2416.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:97" *)
  2417.     casez (i_clk_en)
  2418.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:97" */
  2419.       1'h1:
  2420.           \R_fetch_next$next  = R_disp_early;
  2421.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:109" */
  2422.       default:
  2423.           \R_fetch_next$next  = 1'h0;
  2424.     endcase
  2425.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2426.     casez (pixel_rst)
  2427.       1'h1:
  2428.           \R_fetch_next$next  = 1'h0;
  2429.     endcase
  2430.   end
  2431.   always @* begin
  2432.     \R_disp$next  = R_disp_early;
  2433.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2434.     casez (pixel_rst)
  2435.       1'h1:
  2436.           \R_disp$next  = 1'h0;
  2437.     endcase
  2438.   end
  2439.   always @* begin
  2440.     \R_blank_early$next  = R_blank_early;
  2441.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:119" *)
  2442.     casez ({ \$15 , \$13  })
  2443.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:119" */
  2444.       2'b?1:
  2445.           \R_blank_early$next  = 1'h1;
  2446.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:124" */
  2447.       2'b1?:
  2448.           \R_blank_early$next  = R_vblank;
  2449.     endcase
  2450.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2451.     casez (pixel_rst)
  2452.       1'h1:
  2453.           \R_blank_early$next  = 1'h0;
  2454.     endcase
  2455.   end
  2456.   always @* begin
  2457.     \R_disp_early$next  = R_disp_early;
  2458.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:119" *)
  2459.     casez ({ \$19 , \$17  })
  2460.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:119" */
  2461.       2'b?1:
  2462.           \R_disp_early$next  = 1'h0;
  2463.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:124" */
  2464.       2'b1?:
  2465.           \R_disp_early$next  = R_vdisp;
  2466.     endcase
  2467.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2468.     casez (pixel_rst)
  2469.       1'h1:
  2470.           \R_disp_early$next  = 1'h0;
  2471.     endcase
  2472.   end
  2473.   always @* begin
  2474.     \R_hsync$next  = R_hsync;
  2475.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:129" *)
  2476.     casez ({ \$23 , \$21  })
  2477.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:129" */
  2478.       2'b?1:
  2479.           \R_hsync$next  = 1'h1;
  2480.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:131" */
  2481.       2'b1?:
  2482.           \R_hsync$next  = 1'h0;
  2483.     endcase
  2484.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2485.     casez (pixel_rst)
  2486.       1'h1:
  2487.           \R_hsync$next  = 1'h0;
  2488.     endcase
  2489.   end
  2490.   always @* begin
  2491.     \R_vblank$next  = R_vblank;
  2492.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:134" *)
  2493.     casez ({ \$27 , \$25  })
  2494.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:134" */
  2495.       2'b?1:
  2496.           \R_vblank$next  = 1'h1;
  2497.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:139" */
  2498.       2'b1?:
  2499.           \R_vblank$next  = 1'h0;
  2500.     endcase
  2501.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2502.     casez (pixel_rst)
  2503.       1'h1:
  2504.           \R_vblank$next  = 1'h0;
  2505.     endcase
  2506.   end
  2507.   assign \$3  = \$4 ;
  2508.   assign \$10  = \$11 ;
  2509.   assign \$49  = \$50 ;
  2510.   assign o_vga_de = R_disp;
  2511.   assign o_vga_blank = R_blank;
  2512.   assign o_vga_vsync = R_vsync;
  2513.   assign o_vga_hsync = R_hsync;
  2514.   assign o_vga_b = R_vga_b;
  2515.   assign o_vga_g = R_vga_g;
  2516.   assign o_vga_r = R_vga_r;
  2517.   assign T = { CounterY[6], CounterY[6], CounterY[6], CounterY[6], CounterY[6], CounterY[6], CounterY[6], CounterY[6] };
  2518.   assign Z = \$50 [5:0];
  2519.   assign W = \$45 ;
  2520.   assign A = \$37 ;
  2521.   assign o_fetch_next = R_fetch_next;
  2522.   assign o_beam_y = CounterY;
  2523.   assign o_beam_x = CounterX;
  2524. endmodule
  2525.  
  2526. (* \nmigen.hierarchy  = "top.top.vga2dvid" *)
  2527. (* generator = "nMigen" *)
  2528. module vga2dvid(i_green, i_blue, i_hsync, i_vsync, i_blank, o_clk, o_red, o_green, o_blue, pixel_rst, pixel_clk, shift_clk, i_red);
  2529.   wire [4:0] \$1 ;
  2530.   wire [4:0] \$11 ;
  2531.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" *)
  2532.   wire \$12 ;
  2533.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:165" *)
  2534.   wire [9:0] \$14 ;
  2535.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:168" *)
  2536.   wire \$16 ;
  2537.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:168" *)
  2538.   wire \$18 ;
  2539.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" *)
  2540.   wire \$2 ;
  2541.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:177" *)
  2542.   wire [7:0] \$20 ;
  2543.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:177" *)
  2544.   wire [7:0] \$21 ;
  2545.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:163" *)
  2546.   wire [9:0] \$4 ;
  2547.   wire [4:0] \$6 ;
  2548.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" *)
  2549.   wire \$7 ;
  2550.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:164" *)
  2551.   wire [9:0] \$9 ;
  2552.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:59" *)
  2553.   wire [7:0] R_shift_clock_synchronizer;
  2554.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:60" *)
  2555.   reg [6:0] R_sync_fail = 7'h00;
  2556.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:60" *)
  2557.   reg [6:0] \R_sync_fail$next ;
  2558.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:65" *)
  2559.   wire [7:0] blue_d;
  2560.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:61" *)
  2561.   wire [1:0] c_blue;
  2562.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:47" *)
  2563.   wire [9:0] encoded_blue;
  2564.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:46" *)
  2565.   wire [9:0] encoded_green;
  2566.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:45" *)
  2567.   wire [9:0] encoded_red;
  2568.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:64" *)
  2569.   wire [7:0] green_d;
  2570.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:17" *)
  2571.   input i_blank;
  2572.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:16" *)
  2573.   input [7:0] i_blue;
  2574.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:15" *)
  2575.   input [7:0] i_green;
  2576.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:18" *)
  2577.   input i_hsync;
  2578.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:14" *)
  2579.   input [7:0] i_red;
  2580.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:19" *)
  2581.   input i_vsync;
  2582.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:51" *)
  2583.   reg [9:0] latched_blue = 10'h000;
  2584.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:51" *)
  2585.   reg [9:0] \latched_blue$next ;
  2586.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:50" *)
  2587.   reg [9:0] latched_green = 10'h000;
  2588.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:50" *)
  2589.   reg [9:0] \latched_green$next ;
  2590.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:49" *)
  2591.   reg [9:0] latched_red = 10'h000;
  2592.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:49" *)
  2593.   reg [9:0] \latched_red$next ;
  2594.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:27" *)
  2595.   output [1:0] o_blue;
  2596.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:23" *)
  2597.   wire [9:0] o_blue_par;
  2598.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:28" *)
  2599.   output [1:0] o_clk;
  2600.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:26" *)
  2601.   output [1:0] o_green;
  2602.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:22" *)
  2603.   wire [9:0] o_green_par;
  2604.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:25" *)
  2605.   output [1:0] o_red;
  2606.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:21" *)
  2607.   wire [9:0] o_red_par;
  2608.   (* src = "top_vgatest.py:101" *)
  2609.   input pixel_clk;
  2610.   (* src = "top_vgatest.py:101" *)
  2611.   input pixel_rst;
  2612.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:63" *)
  2613.   wire [7:0] red_d;
  2614.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:55" *)
  2615.   reg [9:0] shift_blue = 10'h000;
  2616.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:55" *)
  2617.   reg [9:0] \shift_blue$next ;
  2618.   (* src = "top_vgatest.py:102" *)
  2619.   input shift_clk;
  2620.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:57" *)
  2621.   reg [9:0] shift_clock = 10'h01f;
  2622.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:57" *)
  2623.   reg [9:0] \shift_clock$next ;
  2624.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:54" *)
  2625.   reg [9:0] shift_green = 10'h000;
  2626.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:54" *)
  2627.   reg [9:0] \shift_green$next ;
  2628.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:53" *)
  2629.   reg [9:0] shift_red = 10'h000;
  2630.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:53" *)
  2631.   reg [9:0] \shift_red$next ;
  2632.   (* src = "top_vgatest.py:102" *)
  2633.   wire shift_rst;
  2634.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:9" *)
  2635.   wire u21_i_blank;
  2636.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:8" *)
  2637.   wire [1:0] u21_i_c;
  2638.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:7" *)
  2639.   wire [7:0] u21_i_data;
  2640.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:10" *)
  2641.   wire [9:0] u21_o_encoded;
  2642.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:9" *)
  2643.   wire u22_i_blank;
  2644.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:8" *)
  2645.   wire [1:0] u22_i_c;
  2646.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:7" *)
  2647.   wire [7:0] u22_i_data;
  2648.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:10" *)
  2649.   wire [9:0] u22_o_encoded;
  2650.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:9" *)
  2651.   wire u23_i_blank;
  2652.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:8" *)
  2653.   wire [1:0] u23_i_c;
  2654.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:7" *)
  2655.   wire [7:0] u23_i_data;
  2656.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:10" *)
  2657.   wire [9:0] u23_o_encoded;
  2658.   assign \$9  = + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:164" *) { 1'h0, shift_green[9:2] };
  2659.   assign \$12  = shift_clock[5:4] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" *) \$11 [4];
  2660.   assign \$14  = + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:165" *) { 1'h0, shift_blue[9:2] };
  2661.   assign \$16  = R_shift_clock_synchronizer[7] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:168" *) 1'h0;
  2662.   assign \$18  = R_shift_clock_synchronizer[7] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:168" *) 1'h0;
  2663.   assign \$21  = R_sync_fail + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:177" *) 1'h1;
  2664.   assign \$2  = shift_clock[5:4] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" *) \$1 [4];
  2665.   assign \$4  = + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:163" *) { 1'h0, shift_red[9:2] };
  2666.   assign \$7  = shift_clock[5:4] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" *) \$6 [4];
  2667.   always @(posedge pixel_clk)
  2668.       latched_red <= \latched_red$next ;
  2669.   always @(posedge shift_clk)
  2670.       R_sync_fail <= \R_sync_fail$next ;
  2671.   always @(posedge shift_clk)
  2672.       shift_clock <= \shift_clock$next ;
  2673.   always @(posedge shift_clk)
  2674.       shift_blue <= \shift_blue$next ;
  2675.   always @(posedge shift_clk)
  2676.       shift_green <= \shift_green$next ;
  2677.   always @(posedge shift_clk)
  2678.       shift_red <= \shift_red$next ;
  2679.   always @(posedge pixel_clk)
  2680.       latched_blue <= \latched_blue$next ;
  2681.   always @(posedge pixel_clk)
  2682.       latched_green <= \latched_green$next ;
  2683.   u21 u21 (
  2684.     .i_blank(u21_i_blank),
  2685.     .i_c(u21_i_c),
  2686.     .i_data(u21_i_data),
  2687.     .o_encoded(u21_o_encoded),
  2688.     .pixel_clk(pixel_clk),
  2689.     .pixel_rst(pixel_rst)
  2690.   );
  2691.   u22 u22 (
  2692.     .i_blank(u22_i_blank),
  2693.     .i_c(u22_i_c),
  2694.     .i_data(u22_i_data),
  2695.     .o_encoded(u22_o_encoded),
  2696.     .pixel_clk(pixel_clk),
  2697.     .pixel_rst(pixel_rst)
  2698.   );
  2699.   u23 u23 (
  2700.     .i_blank(u23_i_blank),
  2701.     .i_c(u23_i_c),
  2702.     .i_data(u23_i_data),
  2703.     .o_encoded(u23_o_encoded),
  2704.     .pixel_clk(pixel_clk),
  2705.     .pixel_rst(pixel_rst)
  2706.   );
  2707.   always @* begin
  2708.     \latched_red$next  = encoded_red;
  2709.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2710.     casez (pixel_rst)
  2711.       1'h1:
  2712.           \latched_red$next  = 10'h000;
  2713.     endcase
  2714.   end
  2715.   always @* begin
  2716.     \latched_green$next  = encoded_green;
  2717.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2718.     casez (pixel_rst)
  2719.       1'h1:
  2720.           \latched_green$next  = 10'h000;
  2721.     endcase
  2722.   end
  2723.   always @* begin
  2724.     \latched_blue$next  = encoded_blue;
  2725.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2726.     casez (pixel_rst)
  2727.       1'h1:
  2728.           \latched_blue$next  = 10'h000;
  2729.     endcase
  2730.   end
  2731.   always @* begin
  2732.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" *)
  2733.     casez (\$2 )
  2734.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" */
  2735.       1'h1:
  2736.           \shift_red$next  = latched_red;
  2737.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:161" */
  2738.       default:
  2739.           \shift_red$next  = \$4 ;
  2740.     endcase
  2741.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2742.     casez (shift_rst)
  2743.       1'h1:
  2744.           \shift_red$next  = 10'h000;
  2745.     endcase
  2746.   end
  2747.   always @* begin
  2748.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" *)
  2749.     casez (\$7 )
  2750.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" */
  2751.       1'h1:
  2752.           \shift_green$next  = latched_green;
  2753.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:161" */
  2754.       default:
  2755.           \shift_green$next  = \$9 ;
  2756.     endcase
  2757.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2758.     casez (shift_rst)
  2759.       1'h1:
  2760.           \shift_green$next  = 10'h000;
  2761.     endcase
  2762.   end
  2763.   always @* begin
  2764.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" *)
  2765.     casez (\$12 )
  2766.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" */
  2767.       1'h1:
  2768.           \shift_blue$next  = latched_blue;
  2769.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:161" */
  2770.       default:
  2771.           \shift_blue$next  = \$14 ;
  2772.     endcase
  2773.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2774.     casez (shift_rst)
  2775.       1'h1:
  2776.           \shift_blue$next  = 10'h000;
  2777.     endcase
  2778.   end
  2779.   always @* begin
  2780.     \shift_clock$next  = shift_clock;
  2781.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:168" *)
  2782.     casez (\$16 )
  2783.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:168" */
  2784.       1'h1:
  2785.           \shift_clock$next  = { shift_clock[1:0], shift_clock[9:2] };
  2786.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:170" */
  2787.       default:
  2788.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:173" *)
  2789.           casez (R_sync_fail[6])
  2790.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:173" */
  2791.             1'h1:
  2792.                 \shift_clock$next  = 10'h01f;
  2793.           endcase
  2794.     endcase
  2795.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2796.     casez (shift_rst)
  2797.       1'h1:
  2798.           \shift_clock$next  = 10'h01f;
  2799.     endcase
  2800.   end
  2801.   always @* begin
  2802.     \R_sync_fail$next  = R_sync_fail;
  2803.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:168" *)
  2804.     casez (\$18 )
  2805.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:168" */
  2806.       1'h1:
  2807.           /* empty */;
  2808.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:170" */
  2809.       default:
  2810.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:173" *)
  2811.           casez (R_sync_fail[6])
  2812.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:173" */
  2813.             1'h1:
  2814.                 \R_sync_fail$next  = 7'h00;
  2815.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:176" */
  2816.             default:
  2817.                 \R_sync_fail$next  = \$20 [6:0];
  2818.           endcase
  2819.     endcase
  2820.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2821.     casez (shift_rst)
  2822.       1'h1:
  2823.           \R_sync_fail$next  = 7'h00;
  2824.     endcase
  2825.   end
  2826.   assign \$1  = 5'h1f;
  2827.   assign \$6  = 5'h1f;
  2828.   assign \$11  = 5'h1f;
  2829.   assign \$20  = \$21 ;
  2830.   assign shift_rst = 1'h0;
  2831.   assign R_shift_clock_synchronizer = 8'h00;
  2832.   assign o_clk = shift_clock[1:0];
  2833.   assign o_blue = shift_blue[1:0];
  2834.   assign o_green = shift_green[1:0];
  2835.   assign o_red = shift_red[1:0];
  2836.   assign o_blue_par = latched_blue;
  2837.   assign o_green_par = latched_green;
  2838.   assign o_red_par = latched_red;
  2839.   assign encoded_blue = u23_o_encoded;
  2840.   assign u23_i_blank = i_blank;
  2841.   assign u23_i_c = c_blue;
  2842.   assign u23_i_data = blue_d;
  2843.   assign encoded_green = u22_o_encoded;
  2844.   assign u22_i_blank = i_blank;
  2845.   assign u22_i_c = 2'h0;
  2846.   assign u22_i_data = green_d;
  2847.   assign encoded_red = u21_o_encoded;
  2848.   assign u21_i_blank = i_blank;
  2849.   assign u21_i_c = 2'h0;
  2850.   assign u21_i_data = red_d;
  2851.   assign blue_d = i_blue;
  2852.   assign green_d = i_green;
  2853.   assign red_d = i_red;
  2854.   assign c_blue = { i_vsync, i_hsync };
  2855. endmodule
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