module counter(input clk_50, input clk_misc, input switch, output ledbit1, output ledbit8);

reg [25:0] counter1, counter2;

always @(posedge clk_50) begin
    counter1 <= counter1 + 1;
end

always @(posedge clk_misc) begin
    counter2 <= counter2 + 1;
end

//assign ledbit1 = counter1[25];
//assign ledbit8 = counter2[25];
assign led = counter1[25:24];
assign lcd_e = 0;

endmodule

---Constraint file---

CONFIG VCCAUX = "3.3";
CONFIG ENABLE_SUSPEND = "FILTERED";
CONFIG POST_CRC = "DISABLE";

NET "lcd_e" LOC = "AB4";

NET "clk_50" LOC = "E12";
NET "clk_misc" LOC = "V12";

net "led<0>" LOC = "R20";
net "led<1>" LOC = "W21";

net "switch" LOC = "T9";