module top(
  input   logic       i_clk,
  input   logic       i_rst_n,
  input   logic [1:0] i_foo,
  output  logic [1:0] o_bar,
  output  logic [1:0] o_baz
);
  if (1) begin : g_bar
    function automatic logic [1:0] f(logic [1:0] v);
      return ~v;
    endfunction
  end

  if (1) begin : g_baz
    function automatic logic [1:0] f(logic [1:0] v);
      return {v[0], v[1]};
    endfunction
  end

  always_ff @(posedge i_clk, negedge i_rst_n) begin
    if (!i_rst_n) begin
      o_bar <= 0;
      o_baz <= 0;
    end
    else begin
      o_bar <= g_bar.f(i_foo);
      o_baz <= g_baz.f(i_foo);
    end
  end
endmodule