module test (
        input  wire [15:0] a,
        input  wire [15:0] b,
        output reg  [15:0] x,
        input  wire [2:0] sel
);


        always @(*)
        begin
                case (sel[1:0])
                        2'b00: x <= a + b;
                        2'b01: x <= b;
                        2'b10: x <= a - b;
                        2'b11: x <= -b;
                endcase
        end

endmodule