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Dec 11th, 2019
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  1. module test (
  2.         input  wire [15:0] a,
  3.         input  wire [15:0] b,
  4.         output reg  [15:0] x,
  5.         input  wire [2:0] sel
  6. );
  7.  
  8.  
  9.         always @(*)
  10.         begin
  11.                 case (sel[1:0])
  12.                         2'b00: x <= a + b;
  13.                         2'b01: x <= b;
  14.                         2'b10: x <= a - b;
  15.                         2'b11: x <= -b;
  16.                 endcase
  17.         end
  18.  
  19. endmodule
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