API tools faq
paste
Guest User

Untitled

a guest
Dec 6th, 2021
92
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 54.09 KB | None | 0 0
raw download clone embed print report
  1. /dts-v1/;
  2.  
  3. / {
  4. compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
  5. #address-cells = <0x2>;
  6. #size-cells = <0x2>;
  7. model = "ZynqMP ZCU102 Rev1.0";
  8.  
  9. cpus {
  10. #address-cells = <0x1>;
  11. #size-cells = <0x0>;
  12.  
  13. cpu@0 {
  14. compatible = "arm,cortex-a53";
  15. device_type = "cpu";
  16. enable-method = "psci";
  17. operating-points-v2 = <0x1>;
  18. reg = <0x0>;
  19. cpu-idle-states = <0x2>;
  20. clocks = <0x3 0xa>;
  21. };
  22.  
  23. cpu@1 {
  24. compatible = "arm,cortex-a53";
  25. device_type = "cpu";
  26. enable-method = "psci";
  27. reg = <0x1>;
  28. operating-points-v2 = <0x1>;
  29. cpu-idle-states = <0x2>;
  30. };
  31.  
  32. cpu@2 {
  33. compatible = "arm,cortex-a53";
  34. device_type = "cpu";
  35. enable-method = "psci";
  36. reg = <0x2>;
  37. operating-points-v2 = <0x1>;
  38. cpu-idle-states = <0x2>;
  39. };
  40.  
  41. cpu@3 {
  42. compatible = "arm,cortex-a53";
  43. device_type = "cpu";
  44. enable-method = "psci";
  45. reg = <0x3>;
  46. operating-points-v2 = <0x1>;
  47. cpu-idle-states = <0x2>;
  48. };
  49.  
  50. idle-states {
  51. entry-method = "psci";
  52.  
  53. cpu-sleep-0 {
  54. compatible = "arm,idle-state";
  55. arm,psci-suspend-param = <0x40000000>;
  56. local-timer-stop;
  57. entry-latency-us = <0x12c>;
  58. exit-latency-us = <0x258>;
  59. min-residency-us = <0x2710>;
  60. phandle = <0x2>;
  61. };
  62. };
  63. };
  64.  
  65. cpu-opp-table {
  66. compatible = "operating-points-v2";
  67. opp-shared;
  68. phandle = <0x1>;
  69.  
  70. opp00 {
  71. opp-hz = <0x0 0x47868bf4>;
  72. opp-microvolt = <0xf4240>;
  73. clock-latency-ns = <0x7a120>;
  74. };
  75.  
  76. opp01 {
  77. opp-hz = <0x0 0x23c345fa>;
  78. opp-microvolt = <0xf4240>;
  79. clock-latency-ns = <0x7a120>;
  80. };
  81.  
  82. opp02 {
  83. opp-hz = <0x0 0x17d783fc>;
  84. opp-microvolt = <0xf4240>;
  85. clock-latency-ns = <0x7a120>;
  86. };
  87.  
  88. opp03 {
  89. opp-hz = <0x0 0x11e1a2fd>;
  90. opp-microvolt = <0xf4240>;
  91. clock-latency-ns = <0x7a120>;
  92. };
  93. };
  94.  
  95. zynqmp_ipi {
  96. u-boot,dm-pre-reloc;
  97. compatible = "xlnx,zynqmp-ipi-mailbox";
  98. interrupt-parent = <0x4>;
  99. interrupts = <0x0 0x23 0x4>;
  100. xlnx,ipi-id = <0x0>;
  101. #address-cells = <0x2>;
  102. #size-cells = <0x2>;
  103. ranges;
  104.  
  105. mailbox@ff990400 {
  106. u-boot,dm-pre-reloc;
  107. reg = <0x0 0xff9905c0 0x0 0x20 0x0 0xff9905e0 0x0 0x20 0x0 0xff990e80 0x0 0x20 0x0 0xff990ea0 0x0 0x20>;
  108. reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region";
  109. #mbox-cells = <0x1>;
  110. xlnx,ipi-id = <0x4>;
  111. phandle = <0x5>;
  112. };
  113. };
  114.  
  115. dcc {
  116. compatible = "arm,dcc";
  117. status = "disabled";
  118. u-boot,dm-pre-reloc;
  119. };
  120.  
  121. pmu {
  122. compatible = "arm,armv8-pmuv3";
  123. interrupt-parent = <0x4>;
  124. interrupts = <0x0 0x8f 0x4 0x0 0x90 0x4 0x0 0x91 0x4 0x0 0x92 0x4>;
  125. };
  126.  
  127. psci {
  128. compatible = "arm,psci-0.2";
  129. method = "smc";
  130. };
  131.  
  132. firmware {
  133.  
  134. zynqmp-firmware {
  135. compatible = "xlnx,zynqmp-firmware";
  136. u-boot,dm-pre-reloc;
  137. method = "smc";
  138. #power-domain-cells = <0x1>;
  139. phandle = <0xc>;
  140.  
  141. zynqmp-power {
  142. u-boot,dm-pre-reloc;
  143. compatible = "xlnx,zynqmp-power";
  144. interrupt-parent = <0x4>;
  145. interrupts = <0x0 0x23 0x4>;
  146. mboxes = <0x5 0x0 0x5 0x1>;
  147. mbox-names = "tx", "rx";
  148. };
  149.  
  150. nvmem_firmware {
  151. compatible = "xlnx,zynqmp-nvmem-fw";
  152. #address-cells = <0x1>;
  153. #size-cells = <0x1>;
  154.  
  155. soc_revision@0 {
  156. reg = <0x0 0x4>;
  157. };
  158.  
  159. efuse_dna@c {
  160. reg = <0xc 0xc>;
  161. };
  162.  
  163. efuse_usr0@20 {
  164. reg = <0x20 0x4>;
  165. };
  166.  
  167. efuse_usr1@24 {
  168. reg = <0x24 0x4>;
  169. };
  170.  
  171. efuse_usr2@28 {
  172. reg = <0x28 0x4>;
  173. };
  174.  
  175. efuse_usr3@2c {
  176. reg = <0x2c 0x4>;
  177. };
  178.  
  179. efuse_usr4@30 {
  180. reg = <0x30 0x4>;
  181. };
  182.  
  183. efuse_usr5@34 {
  184. reg = <0x34 0x4>;
  185. };
  186.  
  187. efuse_usr6@38 {
  188. reg = <0x38 0x4>;
  189. };
  190.  
  191. efuse_usr7@3c {
  192. reg = <0x3c 0x4>;
  193. };
  194.  
  195. efuse_miscusr@40 {
  196. reg = <0x40 0x4>;
  197. };
  198.  
  199. efuse_chash@50 {
  200. reg = <0x50 0x4>;
  201. };
  202.  
  203. efuse_pufmisc@54 {
  204. reg = <0x54 0x4>;
  205. };
  206.  
  207. efuse_sec@58 {
  208. reg = <0x58 0x4>;
  209. };
  210.  
  211. efuse_spkid@5c {
  212. reg = <0x5c 0x4>;
  213. };
  214.  
  215. efuse_ppk0hash@a0 {
  216. reg = <0xa0 0x30>;
  217. };
  218.  
  219. efuse_ppk1hash@d0 {
  220. reg = <0xd0 0x30>;
  221. };
  222. };
  223.  
  224. pcap {
  225. compatible = "xlnx,zynqmp-pcap-fpga";
  226. clock-names = "ref_clk";
  227. clocks = <0x3 0x29>;
  228. phandle = <0xb>;
  229. };
  230.  
  231. zynqmp-aes {
  232. compatible = "xlnx,zynqmp-aes";
  233. };
  234.  
  235. reset-controller {
  236. compatible = "xlnx,zynqmp-reset";
  237. #reset-cells = <0x1>;
  238. phandle = <0x1c>;
  239. };
  240.  
  241. pinctrl {
  242. compatible = "xlnx,zynqmp-pinctrl";
  243. status = "okay";
  244.  
  245. i2c0-default {
  246. phandle = <0x12>;
  247.  
  248. mux {
  249. groups = "i2c0_3_grp";
  250. function = "i2c0";
  251. };
  252.  
  253. conf {
  254. groups = "i2c0_3_grp";
  255. bias-pull-up;
  256. slew-rate = <0x1>;
  257. power-source = <0x1>;
  258. };
  259. };
  260.  
  261. i2c0-gpio {
  262. phandle = <0x13>;
  263.  
  264. mux {
  265. groups = "gpio0_14_grp", "gpio0_15_grp";
  266. function = "gpio0";
  267. };
  268.  
  269. conf {
  270. groups = "gpio0_14_grp", "gpio0_15_grp";
  271. slew-rate = <0x1>;
  272. power-source = <0x1>;
  273. };
  274. };
  275.  
  276. i2c1-default {
  277. phandle = <0x15>;
  278.  
  279. mux {
  280. groups = "i2c1_4_grp";
  281. function = "i2c1";
  282. };
  283.  
  284. conf {
  285. groups = "i2c1_4_grp";
  286. bias-pull-up;
  287. slew-rate = <0x1>;
  288. power-source = <0x1>;
  289. };
  290. };
  291.  
  292. i2c1-gpio {
  293. phandle = <0x16>;
  294.  
  295. mux {
  296. groups = "gpio0_16_grp", "gpio0_17_grp";
  297. function = "gpio0";
  298. };
  299.  
  300. conf {
  301. groups = "gpio0_16_grp", "gpio0_17_grp";
  302. slew-rate = <0x1>;
  303. power-source = <0x1>;
  304. };
  305. };
  306.  
  307. uart0-default {
  308. phandle = <0x3b>;
  309.  
  310. mux {
  311. groups = "uart0_4_grp";
  312. function = "uart0";
  313. };
  314.  
  315. conf {
  316. groups = "uart0_4_grp";
  317. slew-rate = <0x1>;
  318. power-source = <0x1>;
  319. };
  320.  
  321. conf-rx {
  322. pins = "MIO18";
  323. bias-high-impedance;
  324. };
  325.  
  326. conf-tx {
  327. pins = "MIO19";
  328. bias-disable;
  329. };
  330. };
  331.  
  332. uart1-default {
  333. phandle = <0x3c>;
  334.  
  335. mux {
  336. groups = "uart1_5_grp";
  337. function = "uart1";
  338. };
  339.  
  340. conf {
  341. groups = "uart1_5_grp";
  342. slew-rate = <0x1>;
  343. power-source = <0x1>;
  344. };
  345.  
  346. conf-rx {
  347. pins = "MIO21";
  348. bias-high-impedance;
  349. };
  350.  
  351. conf-tx {
  352. pins = "MIO20";
  353. bias-disable;
  354. };
  355. };
  356.  
  357. usb0-default {
  358. phandle = <0x3e>;
  359.  
  360. mux {
  361. groups = "usb0_0_grp";
  362. function = "usb0";
  363. };
  364.  
  365. conf {
  366. groups = "usb0_0_grp";
  367. slew-rate = <0x1>;
  368. power-source = <0x1>;
  369. };
  370.  
  371. conf-rx {
  372. pins = "MIO52", "MIO53", "MIO55";
  373. bias-high-impedance;
  374. };
  375.  
  376. conf-tx {
  377. pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63";
  378. bias-disable;
  379. };
  380. };
  381.  
  382. gem3-default {
  383. phandle = <0x10>;
  384.  
  385. mux {
  386. function = "ethernet3";
  387. groups = "ethernet3_0_grp";
  388. };
  389.  
  390. conf {
  391. groups = "ethernet3_0_grp";
  392. slew-rate = <0x1>;
  393. power-source = <0x1>;
  394. };
  395.  
  396. conf-rx {
  397. pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75";
  398. bias-high-impedance;
  399. low-power-disable;
  400. };
  401.  
  402. conf-tx {
  403. pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69";
  404. bias-disable;
  405. low-power-enable;
  406. };
  407.  
  408. mux-mdio {
  409. function = "mdio3";
  410. groups = "mdio3_0_grp";
  411. };
  412.  
  413. conf-mdio {
  414. groups = "mdio3_0_grp";
  415. slew-rate = <0x1>;
  416. power-source = <0x1>;
  417. bias-disable;
  418. };
  419. };
  420.  
  421. can1-default {
  422. phandle = <0xd>;
  423.  
  424. mux {
  425. function = "can1";
  426. groups = "can1_6_grp";
  427. };
  428.  
  429. conf {
  430. groups = "can1_6_grp";
  431. slew-rate = <0x1>;
  432. power-source = <0x1>;
  433. };
  434.  
  435. conf-rx {
  436. pins = "MIO25";
  437. bias-high-impedance;
  438. };
  439.  
  440. conf-tx {
  441. pins = "MIO24";
  442. bias-disable;
  443. };
  444. };
  445.  
  446. sdhci1-default {
  447. phandle = <0x1e>;
  448.  
  449. mux {
  450. groups = "sdio1_0_grp";
  451. function = "sdio1";
  452. };
  453.  
  454. conf {
  455. groups = "sdio1_0_grp";
  456. slew-rate = <0x1>;
  457. power-source = <0x1>;
  458. bias-disable;
  459. };
  460.  
  461. mux-cd {
  462. groups = "sdio1_cd_0_grp";
  463. function = "sdio1_cd";
  464. };
  465.  
  466. conf-cd {
  467. groups = "sdio1_cd_0_grp";
  468. bias-high-impedance;
  469. bias-pull-up;
  470. slew-rate = <0x1>;
  471. power-source = <0x1>;
  472. };
  473.  
  474. mux-wp {
  475. groups = "sdio1_wp_0_grp";
  476. function = "sdio1_wp";
  477. };
  478.  
  479. conf-wp {
  480. groups = "sdio1_wp_0_grp";
  481. bias-high-impedance;
  482. bias-pull-up;
  483. slew-rate = <0x1>;
  484. power-source = <0x1>;
  485. };
  486. };
  487.  
  488. gpio-default {
  489. phandle = <0x11>;
  490.  
  491. mux-sw {
  492. function = "gpio0";
  493. groups = "gpio0_22_grp", "gpio0_23_grp";
  494. };
  495.  
  496. conf-sw {
  497. groups = "gpio0_22_grp", "gpio0_23_grp";
  498. slew-rate = <0x1>;
  499. power-source = <0x1>;
  500. };
  501.  
  502. mux-msp {
  503. function = "gpio0";
  504. groups = "gpio0_13_grp", "gpio0_38_grp";
  505. };
  506.  
  507. conf-msp {
  508. groups = "gpio0_13_grp", "gpio0_38_grp";
  509. slew-rate = <0x1>;
  510. power-source = <0x1>;
  511. };
  512.  
  513. conf-pull-up {
  514. pins = "MIO22", "MIO23";
  515. bias-pull-up;
  516. };
  517.  
  518. conf-pull-none {
  519. pins = "MIO13", "MIO38";
  520. bias-disable;
  521. };
  522. };
  523. };
  524.  
  525. sha384 {
  526. compatible = "xlnx,zynqmp-keccak-384";
  527. };
  528.  
  529. zynqmp-rsa {
  530. compatible = "xlnx,zynqmp-rsa";
  531. };
  532.  
  533. gpio {
  534. compatible = "xlnx,zynqmp-gpio-modepin";
  535. gpio-controller;
  536. #gpio-cells = <0x2>;
  537. phandle = <0x3d>;
  538. };
  539.  
  540. clock-controller {
  541. u-boot,dm-pre-reloc;
  542. #clock-cells = <0x1>;
  543. compatible = "xlnx,zynqmp-clk";
  544. clocks = <0x6 0x7 0x8 0x9 0xa>;
  545. clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk";
  546. phandle = <0x3>;
  547. };
  548. };
  549. };
  550.  
  551. timer {
  552. compatible = "arm,armv8-timer";
  553. interrupt-parent = <0x4>;
  554. interrupts = <0x1 0xd 0xf08 0x1 0xe 0xf08 0x1 0xb 0xf08 0x1 0xa 0xf08>;
  555. };
  556.  
  557. edac {
  558. compatible = "arm,cortex-a53-edac";
  559. };
  560.  
  561. fpga-full {
  562. compatible = "fpga-region";
  563. fpga-mgr = <0xb>;
  564. #address-cells = <0x2>;
  565. #size-cells = <0x2>;
  566. ranges;
  567. };
  568.  
  569. axi {
  570. compatible = "simple-bus";
  571. u-boot,dm-pre-reloc;
  572. #address-cells = <0x2>;
  573. #size-cells = <0x2>;
  574. ranges;
  575.  
  576. can@ff060000 {
  577. compatible = "xlnx,zynq-can-1.0";
  578. status = "disabled";
  579. clock-names = "can_clk", "pclk";
  580. reg = <0x0 0xff060000 0x0 0x1000>;
  581. interrupts = <0x0 0x17 0x4>;
  582. interrupt-parent = <0x4>;
  583. tx-fifo-depth = <0x40>;
  584. rx-fifo-depth = <0x40>;
  585. power-domains = <0xc 0x2f>;
  586. clocks = <0x3 0x3f 0x3 0x1f>;
  587. };
  588.  
  589. can@ff070000 {
  590. compatible = "xlnx,zynq-can-1.0";
  591. status = "okay";
  592. clock-names = "can_clk", "pclk";
  593. reg = <0x0 0xff070000 0x0 0x1000>;
  594. interrupts = <0x0 0x18 0x4>;
  595. interrupt-parent = <0x4>;
  596. tx-fifo-depth = <0x40>;
  597. rx-fifo-depth = <0x40>;
  598. power-domains = <0xc 0x30>;
  599. clocks = <0x3 0x40 0x3 0x1f>;
  600. pinctrl-names = "default";
  601. pinctrl-0 = <0xd>;
  602. };
  603.  
  604. cci@fd6e0000 {
  605. compatible = "arm,cci-400";
  606. status = "okay";
  607. reg = <0x0 0xfd6e0000 0x0 0x9000>;
  608. ranges = <0x0 0x0 0xfd6e0000 0x10000>;
  609. #address-cells = <0x1>;
  610. #size-cells = <0x1>;
  611.  
  612. pmu@9000 {
  613. compatible = "arm,cci-400-pmu,r1";
  614. reg = <0x9000 0x5000>;
  615. interrupt-parent = <0x4>;
  616. interrupts = <0x0 0x7b 0x4 0x0 0x7b 0x4 0x0 0x7b 0x4 0x0 0x7b 0x4 0x0 0x7b 0x4>;
  617. };
  618. };
  619.  
  620. dma@fd500000 {
  621. status = "okay";
  622. compatible = "xlnx,zynqmp-dma-1.0";
  623. reg = <0x0 0xfd500000 0x0 0x1000>;
  624. interrupt-parent = <0x4>;
  625. interrupts = <0x0 0x7c 0x4>;
  626. clock-names = "clk_main", "clk_apb";
  627. xlnx,bus-width = <0x80>;
  628. #stream-id-cells = <0x1>;
  629. iommus = <0xe 0x14e8>;
  630. power-domains = <0xc 0x2a>;
  631. clocks = <0x3 0x13 0x3 0x1f>;
  632. phandle = <0x2e>;
  633. };
  634.  
  635. dma@fd510000 {
  636. status = "okay";
  637. compatible = "xlnx,zynqmp-dma-1.0";
  638. reg = <0x0 0xfd510000 0x0 0x1000>;
  639. interrupt-parent = <0x4>;
  640. interrupts = <0x0 0x7d 0x4>;
  641. clock-names = "clk_main", "clk_apb";
  642. xlnx,bus-width = <0x80>;
  643. #stream-id-cells = <0x1>;
  644. iommus = <0xe 0x14e9>;
  645. power-domains = <0xc 0x2a>;
  646. clocks = <0x3 0x13 0x3 0x1f>;
  647. phandle = <0x2f>;
  648. };
  649.  
  650. dma@fd520000 {
  651. status = "okay";
  652. compatible = "xlnx,zynqmp-dma-1.0";
  653. reg = <0x0 0xfd520000 0x0 0x1000>;
  654. interrupt-parent = <0x4>;
  655. interrupts = <0x0 0x7e 0x4>;
  656. clock-names = "clk_main", "clk_apb";
  657. xlnx,bus-width = <0x80>;
  658. #stream-id-cells = <0x1>;
  659. iommus = <0xe 0x14ea>;
  660. power-domains = <0xc 0x2a>;
  661. clocks = <0x3 0x13 0x3 0x1f>;
  662. phandle = <0x30>;
  663. };
  664.  
  665. dma@fd530000 {
  666. status = "okay";
  667. compatible = "xlnx,zynqmp-dma-1.0";
  668. reg = <0x0 0xfd530000 0x0 0x1000>;
  669. interrupt-parent = <0x4>;
  670. interrupts = <0x0 0x7f 0x4>;
  671. clock-names = "clk_main", "clk_apb";
  672. xlnx,bus-width = <0x80>;
  673. #stream-id-cells = <0x1>;
  674. iommus = <0xe 0x14eb>;
  675. power-domains = <0xc 0x2a>;
  676. clocks = <0x3 0x13 0x3 0x1f>;
  677. phandle = <0x31>;
  678. };
  679.  
  680. dma@fd540000 {
  681. status = "okay";
  682. compatible = "xlnx,zynqmp-dma-1.0";
  683. reg = <0x0 0xfd540000 0x0 0x1000>;
  684. interrupt-parent = <0x4>;
  685. interrupts = <0x0 0x80 0x4>;
  686. clock-names = "clk_main", "clk_apb";
  687. xlnx,bus-width = <0x80>;
  688. #stream-id-cells = <0x1>;
  689. iommus = <0xe 0x14ec>;
  690. power-domains = <0xc 0x2a>;
  691. clocks = <0x3 0x13 0x3 0x1f>;
  692. phandle = <0x32>;
  693. };
  694.  
  695. dma@fd550000 {
  696. status = "okay";
  697. compatible = "xlnx,zynqmp-dma-1.0";
  698. reg = <0x0 0xfd550000 0x0 0x1000>;
  699. interrupt-parent = <0x4>;
  700. interrupts = <0x0 0x81 0x4>;
  701. clock-names = "clk_main", "clk_apb";
  702. xlnx,bus-width = <0x80>;
  703. #stream-id-cells = <0x1>;
  704. iommus = <0xe 0x14ed>;
  705. power-domains = <0xc 0x2a>;
  706. clocks = <0x3 0x13 0x3 0x1f>;
  707. phandle = <0x33>;
  708. };
  709.  
  710. dma@fd560000 {
  711. status = "okay";
  712. compatible = "xlnx,zynqmp-dma-1.0";
  713. reg = <0x0 0xfd560000 0x0 0x1000>;
  714. interrupt-parent = <0x4>;
  715. interrupts = <0x0 0x82 0x4>;
  716. clock-names = "clk_main", "clk_apb";
  717. xlnx,bus-width = <0x80>;
  718. #stream-id-cells = <0x1>;
  719. iommus = <0xe 0x14ee>;
  720. power-domains = <0xc 0x2a>;
  721. clocks = <0x3 0x13 0x3 0x1f>;
  722. phandle = <0x34>;
  723. };
  724.  
  725. dma@fd570000 {
  726. status = "okay";
  727. compatible = "xlnx,zynqmp-dma-1.0";
  728. reg = <0x0 0xfd570000 0x0 0x1000>;
  729. interrupt-parent = <0x4>;
  730. interrupts = <0x0 0x83 0x4>;
  731. clock-names = "clk_main", "clk_apb";
  732. xlnx,bus-width = <0x80>;
  733. #stream-id-cells = <0x1>;
  734. iommus = <0xe 0x14ef>;
  735. power-domains = <0xc 0x2a>;
  736. clocks = <0x3 0x13 0x3 0x1f>;
  737. phandle = <0x35>;
  738. };
  739.  
  740. interrupt-controller@f9010000 {
  741. compatible = "arm,gic-400";
  742. #interrupt-cells = <0x3>;
  743. reg = <0x0 0xf9010000 0x0 0x10000 0x0 0xf9020000 0x0 0x20000 0x0 0xf9040000 0x0 0x20000 0x0 0xf9060000 0x0 0x20000>;
  744. interrupt-controller;
  745. interrupt-parent = <0x4>;
  746. interrupts = <0x1 0x9 0xf04>;
  747. num_cpus = <0x2>;
  748. num_interrupts = <0x60>;
  749. phandle = <0x4>;
  750. };
  751.  
  752. gpu@fd4b0000 {
  753. status = "okay";
  754. compatible = "arm,mali-400", "arm,mali-utgard";
  755. reg = <0x0 0xfd4b0000 0x0 0x10000>;
  756. interrupt-parent = <0x4>;
  757. interrupts = <0x0 0x84 0x4 0x0 0x84 0x4 0x0 0x84 0x4 0x0 0x84 0x4 0x0 0x84 0x4 0x0 0x84 0x4>;
  758. interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
  759. clock-names = "gpu", "gpu_pp0", "gpu_pp1";
  760. power-domains = <0xc 0x3a>;
  761. clocks = <0x3 0x18 0x3 0x19 0x3 0x1a>;
  762. xlnx,tz-nonsecure = <0x1>;
  763. };
  764.  
  765. dma@ffa80000 {
  766. status = "okay";
  767. compatible = "xlnx,zynqmp-dma-1.0";
  768. reg = <0x0 0xffa80000 0x0 0x1000>;
  769. interrupt-parent = <0x4>;
  770. interrupts = <0x0 0x4d 0x4>;
  771. clock-names = "clk_main", "clk_apb";
  772. xlnx,bus-width = <0x40>;
  773. #stream-id-cells = <0x1>;
  774. power-domains = <0xc 0x2b>;
  775. clocks = <0x3 0x44 0x3 0x1f>;
  776. phandle = <0x26>;
  777. };
  778.  
  779. dma@ffa90000 {
  780. status = "okay";
  781. compatible = "xlnx,zynqmp-dma-1.0";
  782. reg = <0x0 0xffa90000 0x0 0x1000>;
  783. interrupt-parent = <0x4>;
  784. interrupts = <0x0 0x4e 0x4>;
  785. clock-names = "clk_main", "clk_apb";
  786. xlnx,bus-width = <0x40>;
  787. #stream-id-cells = <0x1>;
  788. power-domains = <0xc 0x2b>;
  789. clocks = <0x3 0x44 0x3 0x1f>;
  790. phandle = <0x27>;
  791. };
  792.  
  793. dma@ffaa0000 {
  794. status = "okay";
  795. compatible = "xlnx,zynqmp-dma-1.0";
  796. reg = <0x0 0xffaa0000 0x0 0x1000>;
  797. interrupt-parent = <0x4>;
  798. interrupts = <0x0 0x4f 0x4>;
  799. clock-names = "clk_main", "clk_apb";
  800. xlnx,bus-width = <0x40>;
  801. #stream-id-cells = <0x1>;
  802. power-domains = <0xc 0x2b>;
  803. clocks = <0x3 0x44 0x3 0x1f>;
  804. phandle = <0x28>;
  805. };
  806.  
  807. dma@ffab0000 {
  808. status = "okay";
  809. compatible = "xlnx,zynqmp-dma-1.0";
  810. reg = <0x0 0xffab0000 0x0 0x1000>;
  811. interrupt-parent = <0x4>;
  812. interrupts = <0x0 0x50 0x4>;
  813. clock-names = "clk_main", "clk_apb";
  814. xlnx,bus-width = <0x40>;
  815. #stream-id-cells = <0x1>;
  816. power-domains = <0xc 0x2b>;
  817. clocks = <0x3 0x44 0x3 0x1f>;
  818. phandle = <0x29>;
  819. };
  820.  
  821. dma@ffac0000 {
  822. status = "okay";
  823. compatible = "xlnx,zynqmp-dma-1.0";
  824. reg = <0x0 0xffac0000 0x0 0x1000>;
  825. interrupt-parent = <0x4>;
  826. interrupts = <0x0 0x51 0x4>;
  827. clock-names = "clk_main", "clk_apb";
  828. xlnx,bus-width = <0x40>;
  829. #stream-id-cells = <0x1>;
  830. power-domains = <0xc 0x2b>;
  831. clocks = <0x3 0x44 0x3 0x1f>;
  832. phandle = <0x2a>;
  833. };
  834.  
  835. dma@ffad0000 {
  836. status = "okay";
  837. compatible = "xlnx,zynqmp-dma-1.0";
  838. reg = <0x0 0xffad0000 0x0 0x1000>;
  839. interrupt-parent = <0x4>;
  840. interrupts = <0x0 0x52 0x4>;
  841. clock-names = "clk_main", "clk_apb";
  842. xlnx,bus-width = <0x40>;
  843. #stream-id-cells = <0x1>;
  844. power-domains = <0xc 0x2b>;
  845. clocks = <0x3 0x44 0x3 0x1f>;
  846. phandle = <0x2b>;
  847. };
  848.  
  849. dma@ffae0000 {
  850. status = "okay";
  851. compatible = "xlnx,zynqmp-dma-1.0";
  852. reg = <0x0 0xffae0000 0x0 0x1000>;
  853. interrupt-parent = <0x4>;
  854. interrupts = <0x0 0x53 0x4>;
  855. clock-names = "clk_main", "clk_apb";
  856. xlnx,bus-width = <0x40>;
  857. #stream-id-cells = <0x1>;
  858. power-domains = <0xc 0x2b>;
  859. clocks = <0x3 0x44 0x3 0x1f>;
  860. phandle = <0x2c>;
  861. };
  862.  
  863. dma@ffaf0000 {
  864. status = "okay";
  865. compatible = "xlnx,zynqmp-dma-1.0";
  866. reg = <0x0 0xffaf0000 0x0 0x1000>;
  867. interrupt-parent = <0x4>;
  868. interrupts = <0x0 0x54 0x4>;
  869. clock-names = "clk_main", "clk_apb";
  870. xlnx,bus-width = <0x40>;
  871. #stream-id-cells = <0x1>;
  872. power-domains = <0xc 0x2b>;
  873. clocks = <0x3 0x44 0x3 0x1f>;
  874. phandle = <0x2d>;
  875. };
  876.  
  877. memory-controller@fd070000 {
  878. compatible = "xlnx,zynqmp-ddrc-2.40a";
  879. reg = <0x0 0xfd070000 0x0 0x30000>;
  880. interrupt-parent = <0x4>;
  881. interrupts = <0x0 0x70 0x4>;
  882. };
  883.  
  884. nand-controller@ff100000 {
  885. compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
  886. status = "disabled";
  887. reg = <0x0 0xff100000 0x0 0x1000>;
  888. clock-names = "controller", "bus";
  889. interrupt-parent = <0x4>;
  890. interrupts = <0x0 0xe 0x4>;
  891. #address-cells = <0x1>;
  892. #size-cells = <0x0>;
  893. #stream-id-cells = <0x1>;
  894. iommus = <0xe 0x872>;
  895. power-domains = <0xc 0x2c>;
  896. clocks = <0x3 0x3c 0x3 0x1f>;
  897. phandle = <0x38>;
  898. };
  899.  
  900. ethernet@ff0b0000 {
  901. compatible = "cdns,zynqmp-gem", "cdns,gem";
  902. status = "disabled";
  903. interrupt-parent = <0x4>;
  904. interrupts = <0x0 0x39 0x4 0x0 0x39 0x4>;
  905. reg = <0x0 0xff0b0000 0x0 0x1000>;
  906. clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
  907. #address-cells = <0x1>;
  908. #size-cells = <0x0>;
  909. #stream-id-cells = <0x1>;
  910. iommus = <0xe 0x874>;
  911. power-domains = <0xc 0x1d>;
  912. clocks = <0x3 0x1f 0x3 0x68 0x3 0x2d 0x3 0x31 0x3 0x2c>;
  913. phandle = <0x1f>;
  914. };
  915.  
  916. ethernet@ff0c0000 {
  917. compatible = "cdns,zynqmp-gem", "cdns,gem";
  918. status = "disabled";
  919. interrupt-parent = <0x4>;
  920. interrupts = <0x0 0x3b 0x4 0x0 0x3b 0x4>;
  921. reg = <0x0 0xff0c0000 0x0 0x1000>;
  922. clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
  923. #address-cells = <0x1>;
  924. #size-cells = <0x0>;
  925. #stream-id-cells = <0x1>;
  926. iommus = <0xe 0x875>;
  927. power-domains = <0xc 0x1e>;
  928. clocks = <0x3 0x1f 0x3 0x69 0x3 0x2e 0x3 0x32 0x3 0x2c>;
  929. phandle = <0x20>;
  930. };
  931.  
  932. ethernet@ff0d0000 {
  933. compatible = "cdns,zynqmp-gem", "cdns,gem";
  934. status = "disabled";
  935. interrupt-parent = <0x4>;
  936. interrupts = <0x0 0x3d 0x4 0x0 0x3d 0x4>;
  937. reg = <0x0 0xff0d0000 0x0 0x1000>;
  938. clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
  939. #address-cells = <0x1>;
  940. #size-cells = <0x0>;
  941. #stream-id-cells = <0x1>;
  942. iommus = <0xe 0x876>;
  943. power-domains = <0xc 0x1f>;
  944. clocks = <0x3 0x1f 0x3 0x6a 0x3 0x2f 0x3 0x33 0x3 0x2c>;
  945. phandle = <0x21>;
  946. };
  947.  
  948. ethernet@ff0e0000 {
  949. compatible = "cdns,zynqmp-gem", "cdns,gem";
  950. status = "okay";
  951. interrupt-parent = <0x4>;
  952. interrupts = <0x0 0x3f 0x4 0x0 0x3f 0x4>;
  953. reg = <0x0 0xff0e0000 0x0 0x1000>;
  954. clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
  955. #address-cells = <0x1>;
  956. #size-cells = <0x0>;
  957. #stream-id-cells = <0x1>;
  958. iommus = <0xe 0x877>;
  959. power-domains = <0xc 0x20>;
  960. clocks = <0x3 0x1f 0x3 0x6b 0x3 0x30 0x3 0x34 0x3 0x2c>;
  961. phy-handle = <0xf>;
  962. pinctrl-names = "default";
  963. pinctrl-0 = <0x10>;
  964. phy-mode = "rgmii-id";
  965. xlnx,ptp-enet-clock = <0x0>;
  966. local-mac-address = [ff ff ff ff ff ff];
  967. phandle = <0x22>;
  968.  
  969. ethernet-phy@c {
  970. reg = <0xc>;
  971. ti,rx-internal-delay = <0x8>;
  972. ti,tx-internal-delay = <0xa>;
  973. ti,fifo-depth = <0x1>;
  974. ti,dp83867-rxctrl-strap-quirk;
  975. phandle = <0xf>;
  976. };
  977. };
  978.  
  979. gpio@ff0a0000 {
  980. compatible = "xlnx,zynqmp-gpio-1.0";
  981. status = "okay";
  982. #gpio-cells = <0x2>;
  983. gpio-controller;
  984. interrupt-parent = <0x4>;
  985. interrupts = <0x0 0x10 0x4>;
  986. interrupt-controller;
  987. #interrupt-cells = <0x2>;
  988. reg = <0x0 0xff0a0000 0x0 0x1000>;
  989. power-domains = <0xc 0x2e>;
  990. clocks = <0x3 0x1f>;
  991. pinctrl-names = "default";
  992. pinctrl-0 = <0x11>;
  993. emio-gpio-width = <0x20>;
  994. gpio-mask-high = <0x0>;
  995. gpio-mask-low = <0x5600>;
  996. phandle = <0x14>;
  997. };
  998.  
  999. i2c@ff020000 {
  1000. compatible = "cdns,i2c-r1p14";
  1001. status = "okay";
  1002. interrupt-parent = <0x4>;
  1003. interrupts = <0x0 0x11 0x4>;
  1004. reg = <0x0 0xff020000 0x0 0x1000>;
  1005. #address-cells = <0x1>;
  1006. #size-cells = <0x0>;
  1007. power-domains = <0xc 0x25>;
  1008. clocks = <0x3 0x3d>;
  1009. pinctrl-names = "default", "gpio";
  1010. pinctrl-0 = <0x12>;
  1011. pinctrl-1 = <0x13>;
  1012. scl-gpios = <0x14 0xe 0x0>;
  1013. sda-gpios = <0x14 0xf 0x0>;
  1014. clock-frequency = <0x61a80>;
  1015.  
  1016. gpio@20 {
  1017. compatible = "ti,tca6416";
  1018. reg = <0x20>;
  1019. gpio-controller;
  1020. #gpio-cells = <0x2>;
  1021. gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", "";
  1022. };
  1023.  
  1024. gpio@21 {
  1025. compatible = "ti,tca6416";
  1026. reg = <0x21>;
  1027. gpio-controller;
  1028. #gpio-cells = <0x2>;
  1029. gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
  1030. };
  1031.  
  1032. i2c-mux@75 {
  1033. compatible = "nxp,pca9544";
  1034. #address-cells = <0x1>;
  1035. #size-cells = <0x0>;
  1036. reg = <0x75>;
  1037.  
  1038. i2c@0 {
  1039. #address-cells = <0x1>;
  1040. #size-cells = <0x0>;
  1041. reg = <0x0>;
  1042.  
  1043. ina226@40 {
  1044. compatible = "ti,ina226";
  1045. #io-channel-cells = <0x1>;
  1046. label = "ina226-u76";
  1047. reg = <0x40>;
  1048. shunt-resistor = <0x1388>;
  1049. phandle = <0x43>;
  1050. };
  1051.  
  1052. ina226@41 {
  1053. compatible = "ti,ina226";
  1054. #io-channel-cells = <0x1>;
  1055. label = "ina226-u77";
  1056. reg = <0x41>;
  1057. shunt-resistor = <0x1388>;
  1058. phandle = <0x44>;
  1059. };
  1060.  
  1061. ina226@42 {
  1062. compatible = "ti,ina226";
  1063. #io-channel-cells = <0x1>;
  1064. label = "ina226-u78";
  1065. reg = <0x42>;
  1066. shunt-resistor = <0x1388>;
  1067. phandle = <0x45>;
  1068. };
  1069.  
  1070. ina226@43 {
  1071. compatible = "ti,ina226";
  1072. #io-channel-cells = <0x1>;
  1073. label = "ina226-u87";
  1074. reg = <0x43>;
  1075. shunt-resistor = <0x1388>;
  1076. phandle = <0x46>;
  1077. };
  1078.  
  1079. ina226@44 {
  1080. compatible = "ti,ina226";
  1081. #io-channel-cells = <0x1>;
  1082. label = "ina226-u85";
  1083. reg = <0x44>;
  1084. shunt-resistor = <0x1388>;
  1085. phandle = <0x47>;
  1086. };
  1087.  
  1088. ina226@45 {
  1089. compatible = "ti,ina226";
  1090. #io-channel-cells = <0x1>;
  1091. label = "ina226-u86";
  1092. reg = <0x45>;
  1093. shunt-resistor = <0x1388>;
  1094. phandle = <0x48>;
  1095. };
  1096.  
  1097. ina226@46 {
  1098. compatible = "ti,ina226";
  1099. #io-channel-cells = <0x1>;
  1100. label = "ina226-u93";
  1101. reg = <0x46>;
  1102. shunt-resistor = <0x1388>;
  1103. phandle = <0x49>;
  1104. };
  1105.  
  1106. ina226@47 {
  1107. compatible = "ti,ina226";
  1108. #io-channel-cells = <0x1>;
  1109. label = "ina226-u88";
  1110. reg = <0x47>;
  1111. shunt-resistor = <0x1388>;
  1112. phandle = <0x4a>;
  1113. };
  1114.  
  1115. ina226@4a {
  1116. compatible = "ti,ina226";
  1117. #io-channel-cells = <0x1>;
  1118. label = "ina226-u15";
  1119. reg = <0x4a>;
  1120. shunt-resistor = <0x1388>;
  1121. phandle = <0x4b>;
  1122. };
  1123.  
  1124. ina226@4b {
  1125. compatible = "ti,ina226";
  1126. #io-channel-cells = <0x1>;
  1127. label = "ina226-u92";
  1128. reg = <0x4b>;
  1129. shunt-resistor = <0x1388>;
  1130. phandle = <0x4c>;
  1131. };
  1132. };
  1133.  
  1134. i2c@1 {
  1135. #address-cells = <0x1>;
  1136. #size-cells = <0x0>;
  1137. reg = <0x1>;
  1138.  
  1139. ina226@40 {
  1140. compatible = "ti,ina226";
  1141. #io-channel-cells = <0x1>;
  1142. label = "ina226-u79";
  1143. reg = <0x40>;
  1144. shunt-resistor = <0x7d0>;
  1145. phandle = <0x4d>;
  1146. };
  1147.  
  1148. ina226@41 {
  1149. compatible = "ti,ina226";
  1150. #io-channel-cells = <0x1>;
  1151. label = "ina226-u81";
  1152. reg = <0x41>;
  1153. shunt-resistor = <0x1388>;
  1154. phandle = <0x4e>;
  1155. };
  1156.  
  1157. ina226@42 {
  1158. compatible = "ti,ina226";
  1159. #io-channel-cells = <0x1>;
  1160. label = "ina226-u80";
  1161. reg = <0x42>;
  1162. shunt-resistor = <0x1388>;
  1163. phandle = <0x4f>;
  1164. };
  1165.  
  1166. ina226@43 {
  1167. compatible = "ti,ina226";
  1168. #io-channel-cells = <0x1>;
  1169. label = "ina226-u84";
  1170. reg = <0x43>;
  1171. shunt-resistor = <0x1388>;
  1172. phandle = <0x50>;
  1173. };
  1174.  
  1175. ina226@44 {
  1176. compatible = "ti,ina226";
  1177. #io-channel-cells = <0x1>;
  1178. label = "ina226-u16";
  1179. reg = <0x44>;
  1180. shunt-resistor = <0x1388>;
  1181. phandle = <0x51>;
  1182. };
  1183.  
  1184. ina226@45 {
  1185. compatible = "ti,ina226";
  1186. #io-channel-cells = <0x1>;
  1187. label = "ina226-u65";
  1188. reg = <0x45>;
  1189. shunt-resistor = <0x1388>;
  1190. phandle = <0x52>;
  1191. };
  1192.  
  1193. ina226@46 {
  1194. compatible = "ti,ina226";
  1195. #io-channel-cells = <0x1>;
  1196. label = "ina226-u74";
  1197. reg = <0x46>;
  1198. shunt-resistor = <0x1388>;
  1199. phandle = <0x53>;
  1200. };
  1201.  
  1202. ina226@47 {
  1203. compatible = "ti,ina226";
  1204. #io-channel-cells = <0x1>;
  1205. label = "ina226-u75";
  1206. reg = <0x47>;
  1207. shunt-resistor = <0x1388>;
  1208. phandle = <0x54>;
  1209. };
  1210. };
  1211.  
  1212. i2c@2 {
  1213. #address-cells = <0x1>;
  1214. #size-cells = <0x0>;
  1215. reg = <0x2>;
  1216.  
  1217. max15301@a {
  1218. compatible = "maxim,max15301";
  1219. reg = <0xa>;
  1220. };
  1221.  
  1222. max15303@b {
  1223. compatible = "maxim,max15303";
  1224. reg = <0xb>;
  1225. };
  1226.  
  1227. max15303@10 {
  1228. compatible = "maxim,max15303";
  1229. reg = <0x10>;
  1230. };
  1231.  
  1232. max15301@13 {
  1233. compatible = "maxim,max15301";
  1234. reg = <0x13>;
  1235. };
  1236.  
  1237. max15303@14 {
  1238. compatible = "maxim,max15303";
  1239. reg = <0x14>;
  1240. };
  1241.  
  1242. max15303@15 {
  1243. compatible = "maxim,max15303";
  1244. reg = <0x15>;
  1245. };
  1246.  
  1247. max15303@16 {
  1248. compatible = "maxim,max15303";
  1249. reg = <0x16>;
  1250. };
  1251.  
  1252. max15303@17 {
  1253. compatible = "maxim,max15303";
  1254. reg = <0x17>;
  1255. };
  1256.  
  1257. max15301@18 {
  1258. compatible = "maxim,max15301";
  1259. reg = <0x18>;
  1260. };
  1261.  
  1262. max15303@1a {
  1263. compatible = "maxim,max15303";
  1264. reg = <0x1a>;
  1265. };
  1266.  
  1267. max15303@1b {
  1268. compatible = "maxim,max15303";
  1269. reg = <0x1b>;
  1270. };
  1271.  
  1272. max15303@1d {
  1273. compatible = "maxim,max15303";
  1274. reg = <0x1d>;
  1275. };
  1276.  
  1277. max20751@72 {
  1278. compatible = "maxim,max20751";
  1279. reg = <0x72>;
  1280. };
  1281.  
  1282. max20751@73 {
  1283. compatible = "maxim,max20751";
  1284. reg = <0x73>;
  1285. };
  1286. };
  1287. };
  1288. };
  1289.  
  1290. i2c@ff030000 {
  1291. compatible = "cdns,i2c-r1p14";
  1292. status = "okay";
  1293. interrupt-parent = <0x4>;
  1294. interrupts = <0x0 0x12 0x4>;
  1295. reg = <0x0 0xff030000 0x0 0x1000>;
  1296. #address-cells = <0x1>;
  1297. #size-cells = <0x0>;
  1298. power-domains = <0xc 0x26>;
  1299. clocks = <0x3 0x3e>;
  1300. pinctrl-names = "default", "gpio";
  1301. pinctrl-0 = <0x15>;
  1302. pinctrl-1 = <0x16>;
  1303. scl-gpios = <0x14 0x10 0x0>;
  1304. sda-gpios = <0x14 0x11 0x0>;
  1305. clock-frequency = <0x61a80>;
  1306.  
  1307. i2c-mux@74 {
  1308. compatible = "nxp,pca9548";
  1309. #address-cells = <0x1>;
  1310. #size-cells = <0x0>;
  1311. reg = <0x74>;
  1312.  
  1313. i2c@0 {
  1314. #address-cells = <0x1>;
  1315. #size-cells = <0x0>;
  1316. reg = <0x0>;
  1317.  
  1318. eeprom@54 {
  1319. compatible = "atmel,24c08";
  1320. reg = <0x54>;
  1321. #address-cells = <0x1>;
  1322. #size-cells = <0x1>;
  1323.  
  1324. board-sn@0 {
  1325. reg = <0x0 0x14>;
  1326. };
  1327.  
  1328. eth-mac@20 {
  1329. reg = <0x20 0x6>;
  1330. };
  1331.  
  1332. board-name@d0 {
  1333. reg = <0xd0 0x6>;
  1334. };
  1335.  
  1336. board-revision@e0 {
  1337. reg = <0xe0 0x3>;
  1338. };
  1339. };
  1340. };
  1341.  
  1342. i2c@1 {
  1343. #address-cells = <0x1>;
  1344. #size-cells = <0x0>;
  1345. reg = <0x1>;
  1346.  
  1347. clock-generator@36 {
  1348. compatible = "silabs,si5341";
  1349. reg = <0x36>;
  1350. #clock-cells = <0x2>;
  1351. #address-cells = <0x1>;
  1352. #size-cells = <0x0>;
  1353. clocks = <0x17>;
  1354. clock-names = "xtal";
  1355. clock-output-names = "si5341";
  1356. phandle = <0x1b>;
  1357.  
  1358. out@0 {
  1359. reg = <0x0>;
  1360. always-on;
  1361. };
  1362.  
  1363. out@2 {
  1364. reg = <0x2>;
  1365. always-on;
  1366. };
  1367.  
  1368. out@3 {
  1369. reg = <0x3>;
  1370. always-on;
  1371. };
  1372.  
  1373. out@4 {
  1374. reg = <0x4>;
  1375. always-on;
  1376. };
  1377.  
  1378. out@5 {
  1379. reg = <0x5>;
  1380. always-on;
  1381. };
  1382.  
  1383. out@6 {
  1384. reg = <0x6>;
  1385. always-on;
  1386. };
  1387.  
  1388. out@7 {
  1389. reg = <0x7>;
  1390. always-on;
  1391. };
  1392.  
  1393. out@9 {
  1394. reg = <0x9>;
  1395. always-on;
  1396. };
  1397. };
  1398. };
  1399.  
  1400. i2c@2 {
  1401. #address-cells = <0x1>;
  1402. #size-cells = <0x0>;
  1403. reg = <0x2>;
  1404.  
  1405. clock-generator@5d {
  1406. #clock-cells = <0x0>;
  1407. compatible = "silabs,si570";
  1408. reg = <0x5d>;
  1409. temperature-stability = <0x32>;
  1410. factory-fout = <0x11e1a300>;
  1411. clock-frequency = <0x11e1a300>;
  1412. clock-output-names = "si570_user";
  1413. };
  1414. };
  1415.  
  1416. i2c@3 {
  1417. #address-cells = <0x1>;
  1418. #size-cells = <0x0>;
  1419. reg = <0x3>;
  1420.  
  1421. clock-generator@5d {
  1422. #clock-cells = <0x0>;
  1423. compatible = "silabs,si570";
  1424. reg = <0x5d>;
  1425. temperature-stability = <0x32>;
  1426. factory-fout = <0x9502f90>;
  1427. clock-frequency = <0x8d9ee20>;
  1428. clock-output-names = "si570_mgt";
  1429. };
  1430. };
  1431.  
  1432. i2c@4 {
  1433. #address-cells = <0x1>;
  1434. #size-cells = <0x0>;
  1435. reg = <0x4>;
  1436.  
  1437. clock-generator@69 {
  1438. compatible = "silabs,si5328";
  1439. reg = <0x69>;
  1440. #address-cells = <0x1>;
  1441. #size-cells = <0x0>;
  1442. #clock-cells = <0x1>;
  1443. clocks = <0x18>;
  1444. clock-names = "xtal";
  1445. clock-output-names = "si5328";
  1446.  
  1447. clk0@0 {
  1448. reg = <0x0>;
  1449. clock-frequency = <0x19bfcc0>;
  1450. };
  1451. };
  1452. };
  1453. };
  1454.  
  1455. i2c-mux@75 {
  1456. compatible = "nxp,pca9548";
  1457. #address-cells = <0x1>;
  1458. #size-cells = <0x0>;
  1459. reg = <0x75>;
  1460.  
  1461. i2c@0 {
  1462. #address-cells = <0x1>;
  1463. #size-cells = <0x0>;
  1464. reg = <0x0>;
  1465. };
  1466.  
  1467. i2c@1 {
  1468. #address-cells = <0x1>;
  1469. #size-cells = <0x0>;
  1470. reg = <0x1>;
  1471. };
  1472.  
  1473. i2c@2 {
  1474. #address-cells = <0x1>;
  1475. #size-cells = <0x0>;
  1476. reg = <0x2>;
  1477. };
  1478.  
  1479. i2c@3 {
  1480. #address-cells = <0x1>;
  1481. #size-cells = <0x0>;
  1482. reg = <0x3>;
  1483. };
  1484.  
  1485. i2c@4 {
  1486. #address-cells = <0x1>;
  1487. #size-cells = <0x0>;
  1488. reg = <0x4>;
  1489. };
  1490.  
  1491. i2c@5 {
  1492. #address-cells = <0x1>;
  1493. #size-cells = <0x0>;
  1494. reg = <0x5>;
  1495. };
  1496.  
  1497. i2c@6 {
  1498. #address-cells = <0x1>;
  1499. #size-cells = <0x0>;
  1500. reg = <0x6>;
  1501. };
  1502.  
  1503. i2c@7 {
  1504. #address-cells = <0x1>;
  1505. #size-cells = <0x0>;
  1506. reg = <0x7>;
  1507. };
  1508. };
  1509. };
  1510.  
  1511. memory-controller@ff960000 {
  1512. compatible = "xlnx,zynqmp-ocmc-1.0";
  1513. reg = <0x0 0xff960000 0x0 0x1000>;
  1514. interrupt-parent = <0x4>;
  1515. interrupts = <0x0 0xa 0x4>;
  1516. };
  1517.  
  1518. perf-monitor@ffa00000 {
  1519. compatible = "xlnx,axi-perf-monitor";
  1520. reg = <0x0 0xffa00000 0x0 0x10000>;
  1521. interrupts = <0x0 0x19 0x4>;
  1522. interrupt-parent = <0x4>;
  1523. xlnx,enable-profile = <0x0>;
  1524. xlnx,enable-trace = <0x0>;
  1525. xlnx,num-monitor-slots = <0x1>;
  1526. xlnx,enable-event-count = <0x1>;
  1527. xlnx,enable-event-log = <0x1>;
  1528. xlnx,have-sampled-metric-cnt = <0x1>;
  1529. xlnx,num-of-counters = <0x8>;
  1530. xlnx,metric-count-width = <0x20>;
  1531. xlnx,metrics-sample-count-width = <0x20>;
  1532. xlnx,global-count-width = <0x20>;
  1533. xlnx,metric-count-scale = <0x1>;
  1534. clocks = <0x3 0x1f>;
  1535. };
  1536.  
  1537. perf-monitor@fd0b0000 {
  1538. compatible = "xlnx,axi-perf-monitor";
  1539. reg = <0x0 0xfd0b0000 0x0 0x10000>;
  1540. interrupts = <0x0 0x7b 0x4>;
  1541. interrupt-parent = <0x4>;
  1542. xlnx,enable-profile = <0x0>;
  1543. xlnx,enable-trace = <0x0>;
  1544. xlnx,num-monitor-slots = <0x6>;
  1545. xlnx,enable-event-count = <0x1>;
  1546. xlnx,enable-event-log = <0x0>;
  1547. xlnx,have-sampled-metric-cnt = <0x1>;
  1548. xlnx,num-of-counters = <0xa>;
  1549. xlnx,metric-count-width = <0x20>;
  1550. xlnx,metrics-sample-count-width = <0x20>;
  1551. xlnx,global-count-width = <0x20>;
  1552. xlnx,metric-count-scale = <0x1>;
  1553. clocks = <0x3 0x1c>;
  1554. };
  1555.  
  1556. perf-monitor@fd490000 {
  1557. compatible = "xlnx,axi-perf-monitor";
  1558. reg = <0x0 0xfd490000 0x0 0x10000>;
  1559. interrupts = <0x0 0x7b 0x4>;
  1560. interrupt-parent = <0x4>;
  1561. xlnx,enable-profile = <0x0>;
  1562. xlnx,enable-trace = <0x0>;
  1563. xlnx,num-monitor-slots = <0x1>;
  1564. xlnx,enable-event-count = <0x1>;
  1565. xlnx,enable-event-log = <0x0>;
  1566. xlnx,have-sampled-metric-cnt = <0x1>;
  1567. xlnx,num-of-counters = <0x8>;
  1568. xlnx,metric-count-width = <0x20>;
  1569. xlnx,metrics-sample-count-width = <0x20>;
  1570. xlnx,global-count-width = <0x20>;
  1571. xlnx,metric-count-scale = <0x1>;
  1572. clocks = <0x3 0x1c>;
  1573. };
  1574.  
  1575. perf-monitor@ffa10000 {
  1576. compatible = "xlnx,axi-perf-monitor";
  1577. reg = <0x0 0xffa10000 0x0 0x10000>;
  1578. interrupts = <0x0 0x19 0x4>;
  1579. interrupt-parent = <0x4>;
  1580. xlnx,enable-profile = <0x0>;
  1581. xlnx,enable-trace = <0x0>;
  1582. xlnx,num-monitor-slots = <0x1>;
  1583. xlnx,enable-event-count = <0x1>;
  1584. xlnx,enable-event-log = <0x1>;
  1585. xlnx,have-sampled-metric-cnt = <0x1>;
  1586. xlnx,num-of-counters = <0x8>;
  1587. xlnx,metric-count-width = <0x20>;
  1588. xlnx,metrics-sample-count-width = <0x20>;
  1589. xlnx,global-count-width = <0x20>;
  1590. xlnx,metric-count-scale = <0x1>;
  1591. clocks = <0x3 0x1f>;
  1592. };
  1593.  
  1594. pcie@fd0e0000 {
  1595. compatible = "xlnx,nwl-pcie-2.11";
  1596. status = "okay";
  1597. #address-cells = <0x3>;
  1598. #size-cells = <0x2>;
  1599. #interrupt-cells = <0x1>;
  1600. msi-controller;
  1601. device_type = "pci";
  1602. interrupt-parent = <0x4>;
  1603. interrupts = <0x0 0x76 0x4 0x0 0x75 0x4 0x0 0x74 0x4 0x0 0x73 0x4 0x0 0x72 0x4>;
  1604. interrupt-names = "misc", "dummy", "intx", "msi1", "msi0";
  1605. msi-parent = <0x19>;
  1606. reg = <0x0 0xfd0e0000 0x0 0x1000 0x0 0xfd480000 0x0 0x1000 0x80 0x0 0x0 0x1000000>;
  1607. reg-names = "breg", "pcireg", "cfg";
  1608. ranges = <0x2000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000 0x43000000 0x6 0x0 0x6 0x0 0x2 0x0>;
  1609. interrupt-map-mask = <0x0 0x0 0x0 0x7>;
  1610. bus-range = <0x0 0xff>;
  1611. interrupt-map = <0x0 0x0 0x0 0x1 0x1a 0x1 0x0 0x0 0x0 0x2 0x1a 0x2 0x0 0x0 0x0 0x3 0x1a 0x3 0x0 0x0 0x0 0x4 0x1a 0x4>;
  1612. #stream-id-cells = <0x1>;
  1613. iommus = <0xe 0x4d0>;
  1614. power-domains = <0xc 0x3b>;
  1615. clocks = <0x3 0x17>;
  1616. xlnx,bar0-enable = <0x0>;
  1617. xlnx,bar1-enable = <0x0>;
  1618. xlnx,bar2-enable = <0x0>;
  1619. xlnx,bar3-enable = <0x0>;
  1620. xlnx,bar4-enable = <0x0>;
  1621. xlnx,bar5-enable = <0x0>;
  1622. xlnx,pcie-mode = "Root Port";
  1623. xlnx,tz-nonsecure = <0x0>;
  1624. phandle = <0x19>;
  1625.  
  1626. legacy-interrupt-controller {
  1627. interrupt-controller;
  1628. #address-cells = <0x0>;
  1629. #interrupt-cells = <0x1>;
  1630. phandle = <0x1a>;
  1631. };
  1632. };
  1633.  
  1634. spi@ff0f0000 {
  1635. u-boot,dm-pre-reloc;
  1636. compatible = "xlnx,zynqmp-qspi-1.0";
  1637. status = "okay";
  1638. clock-names = "ref_clk", "pclk";
  1639. interrupts = <0x0 0xf 0x4>;
  1640. interrupt-parent = <0x4>;
  1641. num-cs = <0x1>;
  1642. reg = <0x0 0xff0f0000 0x0 0x1000 0x0 0xc0000000 0x0 0x8000000>;
  1643. #address-cells = <0x1>;
  1644. #size-cells = <0x0>;
  1645. #stream-id-cells = <0x1>;
  1646. iommus = <0xe 0x873>;
  1647. power-domains = <0xc 0x2d>;
  1648. clocks = <0x3 0x35 0x3 0x1f>;
  1649. is-dual = <0x1>;
  1650. spi-rx-bus-width = <0x4>;
  1651. spi-tx-bus-width = <0x4>;
  1652. phandle = <0x25>;
  1653.  
  1654. flash@0 {
  1655. compatible = "m25p80", "jedec,spi-nor";
  1656. #address-cells = <0x1>;
  1657. #size-cells = <0x1>;
  1658. reg = <0x0>;
  1659. spi-tx-bus-width = <0x1>;
  1660. spi-rx-bus-width = <0x4>;
  1661. spi-max-frequency = <0x66ff300>;
  1662.  
  1663. partition@0 {
  1664. label = "boot";
  1665. reg = <0x0 0x1e00000>;
  1666. };
  1667.  
  1668. partition@1 {
  1669. label = "bootenv";
  1670. reg = <0x1e00000 0x40000>;
  1671. };
  1672.  
  1673. partition@2 {
  1674. label = "kernel";
  1675. reg = <0x1e40000 0x2400000>;
  1676. };
  1677. };
  1678. };
  1679.  
  1680. phy@fd400000 {
  1681. compatible = "xlnx,zynqmp-psgtr-v1.1";
  1682. status = "okay";
  1683. reg = <0x0 0xfd400000 0x0 0x40000 0x0 0xfd3d0000 0x0 0x1000>;
  1684. reg-names = "serdes", "siou";
  1685. #phy-cells = <0x4>;
  1686. clocks = <0x1b 0x0 0x5 0x1b 0x0 0x3 0x1b 0x0 0x2 0x1b 0x0 0x0>;
  1687. clock-names = "ref0", "ref1", "ref2", "ref3";
  1688. phandle = <0x1d>;
  1689. };
  1690.  
  1691. rtc@ffa60000 {
  1692. compatible = "xlnx,zynqmp-rtc";
  1693. status = "okay";
  1694. reg = <0x0 0xffa60000 0x0 0x100>;
  1695. interrupt-parent = <0x4>;
  1696. interrupts = <0x0 0x1a 0x4 0x0 0x1b 0x4>;
  1697. interrupt-names = "alarm", "sec";
  1698. calibration = <0x7fff>;
  1699. };
  1700.  
  1701. ahci@fd0c0000 {
  1702. compatible = "ceva,ahci-1v84";
  1703. status = "okay";
  1704. reg = <0x0 0xfd0c0000 0x0 0x2000>;
  1705. interrupt-parent = <0x4>;
  1706. interrupts = <0x0 0x85 0x4>;
  1707. power-domains = <0xc 0x1c>;
  1708. resets = <0x1c 0x10>;
  1709. #stream-id-cells = <0x4>;
  1710. clocks = <0x3 0x16>;
  1711. ceva,p0-cominit-params = <0x18401828>;
  1712. ceva,p0-comwake-params = <0x614080e>;
  1713. ceva,p0-burst-params = <0x13084a06>;
  1714. ceva,p0-retry-params = <0x96a43ffc>;
  1715. ceva,p1-cominit-params = <0x18401828>;
  1716. ceva,p1-comwake-params = <0x614080e>;
  1717. ceva,p1-burst-params = <0x13084a06>;
  1718. ceva,p1-retry-params = <0x96a43ffc>;
  1719. phy-names = "sata-phy";
  1720. phys = <0x1d 0x3 0x1 0x1 0x1>;
  1721. xlnx,tz-nonsecure-sata0 = <0x0>;
  1722. xlnx,tz-nonsecure-sata1 = <0x0>;
  1723. };
  1724.  
  1725. mmc@ff160000 {
  1726. u-boot,dm-pre-reloc;
  1727. compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
  1728. status = "disabled";
  1729. interrupt-parent = <0x4>;
  1730. interrupts = <0x0 0x30 0x4>;
  1731. reg = <0x0 0xff160000 0x0 0x1000>;
  1732. clock-names = "clk_xin", "clk_ahb";
  1733. xlnx,device_id = <0x0>;
  1734. #stream-id-cells = <0x1>;
  1735. iommus = <0xe 0x870>;
  1736. power-domains = <0xc 0x27>;
  1737. #clock-cells = <0x1>;
  1738. clock-output-names = "clk_out_sd0", "clk_in_sd0";
  1739. clocks = <0x3 0x36 0x3 0x1f>;
  1740. phandle = <0x36>;
  1741. };
  1742.  
  1743. mmc@ff170000 {
  1744. u-boot,dm-pre-reloc;
  1745. compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
  1746. status = "okay";
  1747. interrupt-parent = <0x4>;
  1748. interrupts = <0x0 0x31 0x4>;
  1749. reg = <0x0 0xff170000 0x0 0x1000>;
  1750. clock-names = "clk_xin", "clk_ahb";
  1751. xlnx,device_id = <0x1>;
  1752. #stream-id-cells = <0x1>;
  1753. iommus = <0xe 0x871>;
  1754. power-domains = <0xc 0x28>;
  1755. #clock-cells = <0x1>;
  1756. clock-output-names = "clk_out_sd1", "clk_in_sd1";
  1757. clocks = <0x3 0x37 0x3 0x1f>;
  1758. pinctrl-names = "default";
  1759. pinctrl-0 = <0x1e>;
  1760. no-1-8-v;
  1761. clock-frequency = <0xb2cbcae>;
  1762. xlnx,mio-bank = <0x1>;
  1763. phandle = <0x37>;
  1764. };
  1765.  
  1766. smmu@fd800000 {
  1767. compatible = "arm,mmu-500";
  1768. reg = <0x0 0xfd800000 0x0 0x20000>;
  1769. #iommu-cells = <0x1>;
  1770. status = "okay";
  1771. #global-interrupts = <0x1>;
  1772. interrupt-parent = <0x4>;
  1773. interrupts = <0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4>;
  1774. mmu-masters = <0x1f 0x874 0x20 0x875 0x21 0x876 0x22 0x877 0x23 0x860 0x24 0x861 0x25 0x873 0x26 0x868 0x27 0x869 0x28 0x86a 0x29 0x86b 0x2a 0x86c 0x2b 0x86d 0x2c 0x86e 0x2d 0x86f 0x2e 0x14e8 0x2f 0x14e9 0x30 0x14ea 0x31 0x14eb 0x32 0x14ec 0x33 0x14ed 0x34 0x14ee 0x35 0x14ef 0x36 0x870 0x37 0x871 0x38 0x872 0x19 0x4d0 0x39 0xce3 0x3a 0xce4>;
  1775. phandle = <0xe>;
  1776. };
  1777.  
  1778. spi@ff040000 {
  1779. compatible = "cdns,spi-r1p6";
  1780. status = "disabled";
  1781. interrupt-parent = <0x4>;
  1782. interrupts = <0x0 0x13 0x4>;
  1783. reg = <0x0 0xff040000 0x0 0x1000>;
  1784. clock-names = "ref_clk", "pclk";
  1785. #address-cells = <0x1>;
  1786. #size-cells = <0x0>;
  1787. power-domains = <0xc 0x23>;
  1788. clocks = <0x3 0x3a 0x3 0x1f>;
  1789. };
  1790.  
  1791. spi@ff050000 {
  1792. compatible = "cdns,spi-r1p6";
  1793. status = "disabled";
  1794. interrupt-parent = <0x4>;
  1795. interrupts = <0x0 0x14 0x4>;
  1796. reg = <0x0 0xff050000 0x0 0x1000>;
  1797. clock-names = "ref_clk", "pclk";
  1798. #address-cells = <0x1>;
  1799. #size-cells = <0x0>;
  1800. power-domains = <0xc 0x24>;
  1801. clocks = <0x3 0x3b 0x3 0x1f>;
  1802. };
  1803.  
  1804. timer@ff110000 {
  1805. compatible = "cdns,ttc";
  1806. status = "disabled";
  1807. interrupt-parent = <0x4>;
  1808. interrupts = <0x0 0x24 0x4 0x0 0x25 0x4 0x0 0x26 0x4>;
  1809. reg = <0x0 0xff110000 0x0 0x1000>;
  1810. timer-width = <0x20>;
  1811. power-domains = <0xc 0x18>;
  1812. clocks = <0x3 0x1f>;
  1813. };
  1814.  
  1815. timer@ff120000 {
  1816. compatible = "cdns,ttc";
  1817. status = "disabled";
  1818. interrupt-parent = <0x4>;
  1819. interrupts = <0x0 0x27 0x4 0x0 0x28 0x4 0x0 0x29 0x4>;
  1820. reg = <0x0 0xff120000 0x0 0x1000>;
  1821. timer-width = <0x20>;
  1822. power-domains = <0xc 0x19>;
  1823. clocks = <0x3 0x1f>;
  1824. };
  1825.  
  1826. timer@ff130000 {
  1827. compatible = "cdns,ttc";
  1828. status = "disabled";
  1829. interrupt-parent = <0x4>;
  1830. interrupts = <0x0 0x2a 0x4 0x0 0x2b 0x4 0x0 0x2c 0x4>;
  1831. reg = <0x0 0xff130000 0x0 0x1000>;
  1832. timer-width = <0x20>;
  1833. power-domains = <0xc 0x1a>;
  1834. clocks = <0x3 0x1f>;
  1835. };
  1836.  
  1837. timer@ff140000 {
  1838. compatible = "cdns,ttc";
  1839. status = "disabled";
  1840. interrupt-parent = <0x4>;
  1841. interrupts = <0x0 0x2d 0x4 0x0 0x2e 0x4 0x0 0x2f 0x4>;
  1842. reg = <0x0 0xff140000 0x0 0x1000>;
  1843. timer-width = <0x20>;
  1844. power-domains = <0xc 0x1b>;
  1845. clocks = <0x3 0x1f>;
  1846. };
  1847.  
  1848. serial@ff000000 {
  1849. u-boot,dm-pre-reloc;
  1850. compatible = "cdns,uart-r1p12", "xlnx,xuartps";
  1851. status = "okay";
  1852. interrupt-parent = <0x4>;
  1853. interrupts = <0x0 0x15 0x4>;
  1854. reg = <0x0 0xff000000 0x0 0x1000>;
  1855. clock-names = "uart_clk", "pclk";
  1856. power-domains = <0xc 0x21>;
  1857. clocks = <0x3 0x38 0x3 0x1f>;
  1858. pinctrl-names = "default";
  1859. pinctrl-0 = <0x3b>;
  1860. cts-override;
  1861. device_type = "serial";
  1862. port-number = <0x0>;
  1863. };
  1864.  
  1865. serial@ff010000 {
  1866. u-boot,dm-pre-reloc;
  1867. compatible = "cdns,uart-r1p12", "xlnx,xuartps";
  1868. status = "okay";
  1869. interrupt-parent = <0x4>;
  1870. interrupts = <0x0 0x16 0x4>;
  1871. reg = <0x0 0xff010000 0x0 0x1000>;
  1872. clock-names = "uart_clk", "pclk";
  1873. power-domains = <0xc 0x22>;
  1874. clocks = <0x3 0x39 0x3 0x1f>;
  1875. pinctrl-names = "default";
  1876. pinctrl-0 = <0x3c>;
  1877. cts-override;
  1878. device_type = "serial";
  1879. port-number = <0x1>;
  1880. };
  1881.  
  1882. usb0@ff9d0000 {
  1883. #address-cells = <0x2>;
  1884. #size-cells = <0x2>;
  1885. status = "okay";
  1886. compatible = "xlnx,zynqmp-dwc3";
  1887. reg = <0x0 0xff9d0000 0x0 0x100>;
  1888. clock-names = "bus_clk", "ref_clk";
  1889. power-domains = <0xc 0x16>;
  1890. resets = <0x1c 0x3b 0x1c 0x3d 0x1c 0x3f>;
  1891. reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
  1892. reset-gpio = <0x3d 0x1 0x0>;
  1893. ranges;
  1894. clocks = <0x3 0x20 0x3 0x22>;
  1895. pinctrl-names = "default";
  1896. pinctrl-0 = <0x3e>;
  1897. phy-names = "usb3-phy";
  1898. phys = <0x1d 0x2 0x4 0x0 0x2>;
  1899. xlnx,tz-nonsecure = <0x1>;
  1900. xlnx,usb-polarity = <0x0>;
  1901. xlnx,usb-reset-mode = <0x0>;
  1902.  
  1903. dwc3@fe200000 {
  1904. compatible = "snps,dwc3";
  1905. status = "okay";
  1906. reg = <0x0 0xfe200000 0x0 0x40000>;
  1907. interrupt-parent = <0x4>;
  1908. interrupt-names = "dwc_usb3", "otg", "hiber";
  1909. interrupts = <0x0 0x41 0x4 0x0 0x45 0x4 0x0 0x4b 0x4>;
  1910. #stream-id-cells = <0x1>;
  1911. iommus = <0xe 0x860>;
  1912. snps,quirk-frame-length-adjustment = <0x20>;
  1913. snps,refclk_fladj;
  1914. snps,enable_guctl1_resume_quirk;
  1915. snps,enable_guctl1_ipd_quirk;
  1916. snps,xhci-stream-quirk;
  1917. dr_mode = "host";
  1918. snps,usb3_lpm_capable;
  1919. maximum-speed = "super-speed";
  1920. phandle = <0x23>;
  1921. };
  1922. };
  1923.  
  1924. usb1@ff9e0000 {
  1925. #address-cells = <0x2>;
  1926. #size-cells = <0x2>;
  1927. status = "disabled";
  1928. compatible = "xlnx,zynqmp-dwc3";
  1929. reg = <0x0 0xff9e0000 0x0 0x100>;
  1930. clock-names = "bus_clk", "ref_clk";
  1931. power-domains = <0xc 0x17>;
  1932. resets = <0x1c 0x3c 0x1c 0x3e 0x1c 0x40>;
  1933. reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
  1934. ranges;
  1935. clocks = <0x3 0x21 0x3 0x22>;
  1936.  
  1937. dwc3@fe300000 {
  1938. compatible = "snps,dwc3";
  1939. status = "disabled";
  1940. reg = <0x0 0xfe300000 0x0 0x40000>;
  1941. interrupt-parent = <0x4>;
  1942. interrupt-names = "dwc_usb3", "otg", "hiber";
  1943. interrupts = <0x0 0x46 0x4 0x0 0x4a 0x4 0x0 0x4c 0x4>;
  1944. #stream-id-cells = <0x1>;
  1945. iommus = <0xe 0x861>;
  1946. snps,quirk-frame-length-adjustment = <0x20>;
  1947. snps,refclk_fladj;
  1948. snps,enable_guctl1_resume_quirk;
  1949. snps,enable_guctl1_ipd_quirk;
  1950. snps,xhci-stream-quirk;
  1951. phandle = <0x24>;
  1952. };
  1953. };
  1954.  
  1955. watchdog@fd4d0000 {
  1956. compatible = "cdns,wdt-r1p2";
  1957. status = "okay";
  1958. interrupt-parent = <0x4>;
  1959. interrupts = <0x0 0x71 0x1>;
  1960. reg = <0x0 0xfd4d0000 0x0 0x1000>;
  1961. timeout-sec = <0x3c>;
  1962. reset-on-timeout;
  1963. clocks = <0x3 0x4b>;
  1964. };
  1965.  
  1966. watchdog@ff150000 {
  1967. compatible = "cdns,wdt-r1p2";
  1968. status = "okay";
  1969. interrupt-parent = <0x4>;
  1970. interrupts = <0x0 0x34 0x1>;
  1971. reg = <0x0 0xff150000 0x0 0x1000>;
  1972. timeout-sec = <0xa>;
  1973. clocks = <0x3 0x70>;
  1974. };
  1975.  
  1976. ams@ffa50000 {
  1977. compatible = "xlnx,zynqmp-ams";
  1978. status = "okay";
  1979. interrupt-parent = <0x4>;
  1980. interrupts = <0x0 0x38 0x4>;
  1981. interrupt-names = "ams-irq";
  1982. reg = <0x0 0xffa50000 0x0 0x800>;
  1983. reg-names = "ams-base";
  1984. #address-cells = <0x2>;
  1985. #size-cells = <0x2>;
  1986. #io-channel-cells = <0x1>;
  1987. ranges;
  1988. clocks = <0x3 0x46>;
  1989.  
  1990. ams_ps@ffa50800 {
  1991. compatible = "xlnx,zynqmp-ams-ps";
  1992. status = "okay";
  1993. reg = <0x0 0xffa50800 0x0 0x400>;
  1994. };
  1995.  
  1996. ams_pl@ffa50c00 {
  1997. compatible = "xlnx,zynqmp-ams-pl";
  1998. status = "okay";
  1999. reg = <0x0 0xffa50c00 0x0 0x400>;
  2000. };
  2001. };
  2002.  
  2003. dma-controller@fd4c0000 {
  2004. compatible = "xlnx,zynqmp-dpdma";
  2005. status = "okay";
  2006. reg = <0x0 0xfd4c0000 0x0 0x1000>;
  2007. interrupts = <0x0 0x7a 0x4>;
  2008. interrupt-parent = <0x4>;
  2009. clock-names = "axi_clk";
  2010. power-domains = <0xc 0x29>;
  2011. dma-channels = <0x6>;
  2012. #stream-id-cells = <0x1>;
  2013. iommus = <0xe 0xce4>;
  2014. #dma-cells = <0x1>;
  2015. clocks = <0x3 0x14>;
  2016. phandle = <0x3a>;
  2017. };
  2018.  
  2019. display@fd4a0000 {
  2020. compatible = "xlnx,zynqmp-dpsub-1.7";
  2021. status = "okay";
  2022. reg = <0x0 0xfd4a0000 0x0 0x1000 0x0 0xfd4aa000 0x0 0x1000 0x0 0xfd4ab000 0x0 0x1000 0x0 0xfd4ac000 0x0 0x1000>;
  2023. reg-names = "dp", "blend", "av_buf", "aud";
  2024. interrupts = <0x0 0x77 0x4>;
  2025. interrupt-parent = <0x4>;
  2026. #stream-id-cells = <0x1>;
  2027. iommus = <0xe 0xce3>;
  2028. clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in";
  2029. power-domains = <0xc 0x29>;
  2030. resets = <0x1c 0x3>;
  2031. dma-names = "vid0", "vid1", "vid2", "gfx0";
  2032. dmas = <0x3a 0x0 0x3a 0x1 0x3a 0x2 0x3a 0x3>;
  2033. clocks = <0x3f 0x3 0x11 0x3 0x10>;
  2034. phy-names = "dp-phy0";
  2035. phys = <0x1d 0x1 0x6 0x0 0x3>;
  2036. xlnx,max-lanes = <0x1>;
  2037. phandle = <0x39>;
  2038.  
  2039. i2c-bus {
  2040. };
  2041.  
  2042. zynqmp_dp_snd_codec0 {
  2043. compatible = "xlnx,dp-snd-codec";
  2044. clock-names = "aud_clk";
  2045. clocks = <0x3 0x11>;
  2046. status = "okay";
  2047. phandle = <0x42>;
  2048. };
  2049.  
  2050. zynqmp_dp_snd_pcm0 {
  2051. compatible = "xlnx,dp-snd-pcm0";
  2052. dmas = <0x3a 0x4>;
  2053. dma-names = "tx";
  2054. status = "okay";
  2055. phandle = <0x40>;
  2056. };
  2057.  
  2058. zynqmp_dp_snd_pcm1 {
  2059. compatible = "xlnx,dp-snd-pcm1";
  2060. dmas = <0x3a 0x5>;
  2061. dma-names = "tx";
  2062. status = "okay";
  2063. phandle = <0x41>;
  2064. };
  2065.  
  2066. zynqmp_dp_snd_card {
  2067. compatible = "xlnx,dp-snd-card";
  2068. xlnx,dp-snd-pcm = <0x40 0x41>;
  2069. xlnx,dp-snd-codec = <0x42>;
  2070. status = "okay";
  2071. };
  2072. };
  2073. };
  2074.  
  2075. fclk0 {
  2076. status = "okay";
  2077. compatible = "xlnx,fclk";
  2078. clocks = <0x3 0x47>;
  2079. };
  2080.  
  2081. fclk1 {
  2082. status = "okay";
  2083. compatible = "xlnx,fclk";
  2084. clocks = <0x3 0x48>;
  2085. };
  2086.  
  2087. fclk2 {
  2088. status = "okay";
  2089. compatible = "xlnx,fclk";
  2090. clocks = <0x3 0x49>;
  2091. };
  2092.  
  2093. fclk3 {
  2094. status = "okay";
  2095. compatible = "xlnx,fclk";
  2096. clocks = <0x3 0x4a>;
  2097. };
  2098.  
  2099. pss_ref_clk {
  2100. u-boot,dm-pre-reloc;
  2101. compatible = "fixed-clock";
  2102. #clock-cells = <0x0>;
  2103. clock-frequency = <0x1fc9350>;
  2104. phandle = <0x6>;
  2105. };
  2106.  
  2107. video_clk {
  2108. u-boot,dm-pre-reloc;
  2109. compatible = "fixed-clock";
  2110. #clock-cells = <0x0>;
  2111. clock-frequency = <0x1fc9f08>;
  2112. phandle = <0x7>;
  2113. };
  2114.  
  2115. pss_alt_ref_clk {
  2116. u-boot,dm-pre-reloc;
  2117. compatible = "fixed-clock";
  2118. #clock-cells = <0x0>;
  2119. clock-frequency = <0x0>;
  2120. phandle = <0x8>;
  2121. };
  2122.  
  2123. gt_crx_ref_clk {
  2124. u-boot,dm-pre-reloc;
  2125. compatible = "fixed-clock";
  2126. #clock-cells = <0x0>;
  2127. clock-frequency = <0x66ff300>;
  2128. phandle = <0xa>;
  2129. };
  2130.  
  2131. aux_ref_clk {
  2132. u-boot,dm-pre-reloc;
  2133. compatible = "fixed-clock";
  2134. #clock-cells = <0x0>;
  2135. clock-frequency = <0x19bfcc0>;
  2136. phandle = <0x9>;
  2137. };
  2138.  
  2139. dp_aclk {
  2140. compatible = "fixed-clock";
  2141. #clock-cells = <0x0>;
  2142. clock-frequency = <0x5f5e100>;
  2143. clock-accuracy = <0x64>;
  2144. phandle = <0x3f>;
  2145. };
  2146.  
  2147. gpio-keys {
  2148. compatible = "gpio-keys";
  2149. #address-cells = <0x1>;
  2150. #size-cells = <0x0>;
  2151. autorepeat;
  2152.  
  2153. sw19 {
  2154. label = "sw19";
  2155. gpios = <0x14 0x16 0x0>;
  2156. linux,code = <0x6c>;
  2157. wakeup-source;
  2158. autorepeat;
  2159. };
  2160. };
  2161.  
  2162. leds {
  2163. compatible = "gpio-leds";
  2164.  
  2165. heartbeat-led {
  2166. label = "heartbeat";
  2167. gpios = <0x14 0x17 0x0>;
  2168. linux,default-trigger = "heartbeat";
  2169. };
  2170. };
  2171.  
  2172. chosen {
  2173. nvmem0 = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54";
  2174. bootargs = " earlycon console=ttyPS0,115200 clk_ignore_unused init_fatal_sh=1";
  2175. stdout-path = "serial0:115200n8";
  2176. };
  2177.  
  2178. ina226-u76 {
  2179. compatible = "iio-hwmon";
  2180. io-channels = <0x43 0x0 0x43 0x1 0x43 0x2 0x43 0x3>;
  2181. };
  2182.  
  2183. ina226-u77 {
  2184. compatible = "iio-hwmon";
  2185. io-channels = <0x44 0x0 0x44 0x1 0x44 0x2 0x44 0x3>;
  2186. };
  2187.  
  2188. ina226-u78 {
  2189. compatible = "iio-hwmon";
  2190. io-channels = <0x45 0x0 0x45 0x1 0x45 0x2 0x45 0x3>;
  2191. };
  2192.  
  2193. ina226-u87 {
  2194. compatible = "iio-hwmon";
  2195. io-channels = <0x46 0x0 0x46 0x1 0x46 0x2 0x46 0x3>;
  2196. };
  2197.  
  2198. ina226-u85 {
  2199. compatible = "iio-hwmon";
  2200. io-channels = <0x47 0x0 0x47 0x1 0x47 0x2 0x47 0x3>;
  2201. };
  2202.  
  2203. ina226-u86 {
  2204. compatible = "iio-hwmon";
  2205. io-channels = <0x48 0x0 0x48 0x1 0x48 0x2 0x48 0x3>;
  2206. };
  2207.  
  2208. ina226-u93 {
  2209. compatible = "iio-hwmon";
  2210. io-channels = <0x49 0x0 0x49 0x1 0x49 0x2 0x49 0x3>;
  2211. };
  2212.  
  2213. ina226-u88 {
  2214. compatible = "iio-hwmon";
  2215. io-channels = <0x4a 0x0 0x4a 0x1 0x4a 0x2 0x4a 0x3>;
  2216. };
  2217.  
  2218. ina226-u15 {
  2219. compatible = "iio-hwmon";
  2220. io-channels = <0x4b 0x0 0x4b 0x1 0x4b 0x2 0x4b 0x3>;
  2221. };
  2222.  
  2223. ina226-u92 {
  2224. compatible = "iio-hwmon";
  2225. io-channels = <0x4c 0x0 0x4c 0x1 0x4c 0x2 0x4c 0x3>;
  2226. };
  2227.  
  2228. ina226-u79 {
  2229. compatible = "iio-hwmon";
  2230. io-channels = <0x4d 0x0 0x4d 0x1 0x4d 0x2 0x4d 0x3>;
  2231. };
  2232.  
  2233. ina226-u81 {
  2234. compatible = "iio-hwmon";
  2235. io-channels = <0x4e 0x0 0x4e 0x1 0x4e 0x2 0x4e 0x3>;
  2236. };
  2237.  
  2238. ina226-u80 {
  2239. compatible = "iio-hwmon";
  2240. io-channels = <0x4f 0x0 0x4f 0x1 0x4f 0x2 0x4f 0x3>;
  2241. };
  2242.  
  2243. ina226-u84 {
  2244. compatible = "iio-hwmon";
  2245. io-channels = <0x50 0x0 0x50 0x1 0x50 0x2 0x50 0x3>;
  2246. };
  2247.  
  2248. ina226-u16 {
  2249. compatible = "iio-hwmon";
  2250. io-channels = <0x51 0x0 0x51 0x1 0x51 0x2 0x51 0x3>;
  2251. };
  2252.  
  2253. ina226-u65 {
  2254. compatible = "iio-hwmon";
  2255. io-channels = <0x52 0x0 0x52 0x1 0x52 0x2 0x52 0x3>;
  2256. };
  2257.  
  2258. ina226-u74 {
  2259. compatible = "iio-hwmon";
  2260. io-channels = <0x53 0x0 0x53 0x1 0x53 0x2 0x53 0x3>;
  2261. };
  2262.  
  2263. ina226-u75 {
  2264. compatible = "iio-hwmon";
  2265. io-channels = <0x54 0x0 0x54 0x1 0x54 0x2 0x54 0x3>;
  2266. };
  2267.  
  2268. ref48M {
  2269. compatible = "fixed-clock";
  2270. #clock-cells = <0x0>;
  2271. clock-frequency = <0x2dc6c00>;
  2272. phandle = <0x17>;
  2273. };
  2274.  
  2275. refhdmi {
  2276. compatible = "fixed-clock";
  2277. #clock-cells = <0x0>;
  2278. clock-frequency = <0x6cfd9c8>;
  2279. phandle = <0x18>;
  2280. };
  2281.  
  2282. amba_pl@0 {
  2283. #address-cells = <0x2>;
  2284. #size-cells = <0x2>;
  2285. compatible = "simple-bus";
  2286. ranges;
  2287.  
  2288. interrupt-controller@80020000 {
  2289. #interrupt-cells = <0x2>;
  2290. clock-names = "s_axi_aclk";
  2291. clocks = <0x55>;
  2292. compatible = "xlnx,axi-intc-4.1", "xlnx,xps-intc-1.00.a";
  2293. interrupt-controller;
  2294. interrupt-names = "irq";
  2295. interrupt-parent = <0x4>;
  2296. interrupts = <0x0 0x59 0x4>;
  2297. reg = <0x0 0x80020000 0x0 0x1000>;
  2298. xlnx,kind-of-intr = <0x1>;
  2299. xlnx,num-intr-inputs = <0x20>;
  2300. phandle = <0x56>;
  2301. };
  2302.  
  2303. misc_clk_0 {
  2304. #clock-cells = <0x0>;
  2305. clock-frequency = <0x4784b74>;
  2306. compatible = "fixed-clock";
  2307. phandle = <0x55>;
  2308. };
  2309.  
  2310. zyxclmm_drm {
  2311. compatible = "xlnx,zocl";
  2312. interrupts-extended = <0x56 0x0 0x4 0x56 0x1 0x4 0x56 0x2 0x4 0x56 0x3 0x4 0x56 0x4 0x4 0x56 0x5 0x4 0x56 0x6 0x4 0x56 0x7 0x4 0x56 0x8 0x4 0x56 0x9 0x4 0x56 0xa 0x4 0x56 0xb 0x4 0x56 0xc 0x4 0x56 0xd 0x4 0x56 0xe 0x4 0x56 0xf 0x4 0x56 0x10 0x4 0x56 0x11 0x4 0x56 0x12 0x4 0x56 0x13 0x4 0x56 0x14 0x4 0x56 0x15 0x4 0x56 0x16 0x4 0x56 0x17 0x4 0x56 0x18 0x4 0x56 0x19 0x4 0x56 0x1a 0x4 0x56 0x1b 0x4 0x56 0x1c 0x4 0x56 0x1d 0x4 0x56 0x1e 0x4 0x56 0x1f 0x4>;
  2313. };
  2314. };
  2315.  
  2316. aliases {
  2317. ethernet0 = "/axi/ethernet@ff0e0000";
  2318. i2c0 = "/axi/i2c@ff020000";
  2319. i2c1 = "/axi/i2c@ff030000";
  2320. serial0 = "/axi/serial@ff000000";
  2321. serial1 = "/axi/serial@ff010000";
  2322. spi0 = "/axi/spi@ff0f0000";
  2323. };
  2324.  
  2325. memory {
  2326. device_type = "memory";
  2327. reg = <0x0 0x0 0x0 0x7ff00000 0x8 0x0 0x0 0x80000000>;
  2328. };
  2329. };
  2330.  
Add Comment
Please, Sign In to add comment
Public Pastes
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!