entity FDN is
generic (n: natural := 32);
  port (
  D : in std_logic_vector(n-1 downto 0 );
  Clk: in std_logic;
  Rst: in std_logic;
  Ce: in std_logic;
  Q : out std_logic_vector(n-1 downto 0 )
  );
end FDN;

architecture Behavioral of FDN is

begin

process(Clk)
begin
 if(rising_edge(Clk)) then
    if(Rst='1') then
     Q<= (others => '0');
   else
     if( Ce='1') then
       Q<=D;
     end if;
   end if;
 end if;
end process;
end Behavioral;