`timescale 1ns/1ps

module DZ_test;

logic clk, sclr;
reg [2:0] q;

initial
begin
    clk=0;
    forever #10 clk = ~clk;
end
initial
begin
    sclr = 1;
    #50 sclr = ~sclr;
    #60 sclr = ~sclr;
    #70 sclr = ~sclr;
    #80 sclr = ~sclr;
    #100 sclr = ~sclr;
    #300 $stop;
end
DZ uut_inst(clk, sclr, q);
endmodule