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-- Company:
-- Engineer:
--
-- Create Date:    10:35:26 04/12/2016
-- Design Name:
-- Module Name:    cw6 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY disp_tb IS
END disp_tb;

ARCHITECTURE behavior OF disp_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT cw6
    PORT(
         clk_i : IN  std_logic;
         led7_seg_o : OUT  std_logic_vector(7 downto 0);
         led7_an_o : OUT  std_logic_vector(3 downto 0);
         sw_i : IN  std_logic_vector(7 downto 0);
         btn_i : IN  std_logic_vector(3 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal clk_i : std_logic := '0';
   signal sw_i : std_logic_vector(7 downto 0) := (others => '0');
   signal btn_i : std_logic_vector(3 downto 0) := (others => '0');

 	--Outputs
   signal led7_seg_o : std_logic_vector(7 downto 0);
   signal led7_an_o : std_logic_vector(3 downto 0);

   -- Clock period definitions
   constant clk_i_period : time := 1 ns;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
   uut: top PORT MAP (
          clk_i => clk_i,
          led7_seg_o => led7_seg_o,
          led7_an_o => led7_an_o,
          sw_i => sw_i,
          btn_i => btn_i
        );

   -- Clock process definitions
   clk_i_process :process
   begin
		clk_i <= '0';
		wait for clk_i_period/2;
		clk_i <= '1';
		wait for clk_i_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100ms.
      wait for 100 ns;
		sw_i <= "11110011";
		wait for 10 ns;
		btn_i <= "1000";
		wait for 10 ns;
		btn_i <= "0000"
		wait for 100 ns;
		swi_i <= "11000001";
		wait for 10 ns;
		btn_i <= "0100";
		wait for 10 ns;
		btn_i <= "0000";
		wait for 10 ns;


      wait;
   end process;

END;