Booth

module booth

#( parameter OPERAND_BITS = 8,
parameter RESULT_BITS = 16)

(
input clk,
input rst,
input start,

input [OPERAND_BITS - 1 : 0] a,
input [OPERAND_BITS - 1 : 0] b,

output[RESULT_BITS - 1 : 0] result

);

reg [OPERAND_BITS - 1 : 0] A;
reg [OPERAND_BITS - 1 : 0] M;
reg [OPERAND_BITS - 1 : -1] Q;
reg [2:0] count;

localparam [2:0] WAIT=3'd0, INIT=3'd1, ADD=3'd2, SUB=3'd3, SHIFT=3'd4, END=3'd5;

reg [1:0] state;
reg [1:0] state_nxt;

wire [1:0] Q01= {Q[0],Q[-1]};




// sequential process

always

@(posedge clk)
begin
  case(state)
    WAIT: ;
    INIT:
      begin
        A <= 0;
        count <= 0;
        M <= a;
        Q <= b;
        Q[-1] <= 0;
      end
    ADD:
      begin
        A = A + M;
      end
    SUB:
      begin
        A = A - M;
      end
    SHIFT:
      begin
        A[7] = A[7];
       {A[6:0],Q} = {A,Q[7:0]};
        count = count + 1;
      end
  endcase

// do something

end

always @(posedge clk or negedge rst)
begin
  if(rst)
    state <= WAIT;
  else
    state <= state_nxt;
end



// combinational process

always

@(start, Q01)

begin

// create state machine
  case(state)
    WAIT:
      if(start)
        state_nxt = INIT;
      else
        state_nxt = WAIT;
    INIT:
      if(Q01 == 2'b0_1)
        state_nxt = ADD;
      else
        state_nxt = SUB;
    ADD:
      if(count)
        state_nxt = END;
      else
        state_nxt = SHIFT;
    SUB:
      if(count)
        state_nxt = END;
      else
        state_nxt = SHIFT;
    SHIFT:
      if(Q01 == 2'b0_1)
        state_nxt = ADD;
      else
        state_nxt = SUB;

    END: ;
  endcase
// determine values for all signals in each state

end

assign result = {A, Q[7:0]};

endmodule