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  1.  
  2. #define ARM_BUS0_BASE 0x18000000
  3. #define ARM_BUS1_BASE 0x18400000
  4.  
  5. /* SCU module */
  6. #define APB0_SCU (ARM_BUS0_BASE + 0x0001C000)
  7. #define SCU_ID (*(volatile unsigned long *)(APB0_SCU + 0x00))
  8. #define SCU_REMAP (*(volatile unsigned long *)(APB0_SCU + 0x04))
  9. #define SCU_PLLCON1 (*(volatile unsigned long *)(APB0_SCU + 0x08))
  10. #define SCU_PLLCON2 (*(volatile unsigned long *)(APB0_SCU + 0x0C))
  11. #define SCU_PLLCON3 (*(volatile unsigned long *)(APB0_SCU + 0x10))
  12. #define SCU_DIVCON1 (*(volatile unsigned long *)(APB0_SCU + 0x14))
  13. #define SCU_CLKCFG (*(volatile unsigned long *)(APB0_SCU + 0x18))
  14. #define SCU_RSTCFG (*(volatile unsigned long *)(APB0_SCU + 0x1C))
  15. #define SCU_PWM (*(volatile unsigned long *)(APB0_SCU + 0x20))
  16. #define SCU_CPUPD (*(volatile unsigned long *)(APB0_SCU + 0x24))
  17. #define SCU_CHIPCFG (*(volatile unsigned long *)(APB0_SCU + 0x28))
  18. #define SCU_STATUS (*(volatile unsigned long *)(APB0_SCU + 0x2C))
  19. #define SCU_IOMUXA_CON (*(volatile unsigned long *)(APB0_SCU + 0x30))
  20.  
  21.  
  22. #define SCU_IOMUXB_CON (*(volatile unsigned long *)(APB0_SCU + 0x34))
  23.  
  24. #define SCU_GPIOUPCON (*(volatile unsigned long *)(APB0_SCU + 0x38))
  25. #define SCU_DIVCON2 (*(volatile unsigned long *)(APB0_SCU + 0x3C))
  26.  
  27.  
  28. /* Interrupt controller */
  29. #define AHB0_INTC (ARM_BUS0_BASE + 0x00080000)
  30. #define INTC_SCR0 (*(volatile unsigned long *)(AHB0_INTC + 0x00))
  31. #define INTC_SCR1 (*(volatile unsigned long *)(AHB0_INTC + 0x04))
  32. #define INTC_SCR2 (*(volatile unsigned long *)(AHB0_INTC + 0x08))
  33. #define INTC_SCR3 (*(volatile unsigned long *)(AHB0_INTC + 0x0C))
  34. #define INTC_SCR4 (*(volatile unsigned long *)(AHB0_INTC + 0x10))
  35. #define INTC_SCR5 (*(volatile unsigned long *)(AHB0_INTC + 0x14))
  36. #define INTC_SCR6 (*(volatile unsigned long *)(AHB0_INTC + 0x18))
  37. #define INTC_SCR7 (*(volatile unsigned long *)(AHB0_INTC + 0x1C))
  38. #define INTC_SCR8 (*(volatile unsigned long *)(AHB0_INTC + 0x20))
  39. #define INTC_SCR9 (*(volatile unsigned long *)(AHB0_INTC + 0x24))
  40. #define INTC_SCR10 (*(volatile unsigned long *)(AHB0_INTC + 0x28))
  41. #define INTC_SCR11 (*(volatile unsigned long *)(AHB0_INTC + 0x2C))
  42. #define INTC_SCR12 (*(volatile unsigned long *)(AHB0_INTC + 0x30))
  43. #define INTC_SCR13 (*(volatile unsigned long *)(AHB0_INTC + 0x34))
  44. #define INTC_SCR14 (*(volatile unsigned long *)(AHB0_INTC + 0x38))
  45. #define INTC_SCR15 (*(volatile unsigned long *)(AHB0_INTC + 0x3C))
  46. #define INTC_SCR16 (*(volatile unsigned long *)(AHB0_INTC + 0x40))
  47. #define INTC_SCR17 (*(volatile unsigned long *)(AHB0_INTC + 0x44))
  48. #define INTC_SCR18 (*(volatile unsigned long *)(AHB0_INTC + 0x48))
  49. #define INTC_SCR19 (*(volatile unsigned long *)(AHB0_INTC + 0x4C))
  50. #define INTC_SCR20 (*(volatile unsigned long *)(AHB0_INTC + 0x50))
  51. #define INTC_SCR21 (*(volatile unsigned long *)(AHB0_INTC + 0x54))
  52. #define INTC_SCR22 (*(volatile unsigned long *)(AHB0_INTC + 0x58))
  53. #define INTC_SCR23 (*(volatile unsigned long *)(AHB0_INTC + 0x5C))
  54. #define INTC_SCR24 (*(volatile unsigned long *)(AHB0_INTC + 0x60))
  55. #define INTC_SCR25 (*(volatile unsigned long *)(AHB0_INTC + 0x64))
  56. #define INTC_SCR26 (*(volatile unsigned long *)(AHB0_INTC + 0x68))
  57. #define INTC_SCR27 (*(volatile unsigned long *)(AHB0_INTC + 0x6C))
  58. #define INTC_SCR28 (*(volatile unsigned long *)(AHB0_INTC + 0x70))
  59. #define INTC_SCR29 (*(volatile unsigned long *)(AHB0_INTC + 0x74))
  60. #define INTC_SCR30 (*(volatile unsigned long *)(AHB0_INTC + 0x78))
  61. #define INTC_SCR31 (*(volatile unsigned long *)(AHB0_INTC + 0x7C))
  62.  
  63. #define INTC_ISR (*(volatile unsigned long *)(AHB0_INTC + 0x104))
  64. #define INTC_IPR (*(volatile unsigned long *)(AHB0_INTC + 0x108))
  65. #define INTC_IMR (*(volatile unsigned long *)(AHB0_INTC + 0x10C))
  66.  
  67. #define INTC_IECR (*(volatile unsigned long *)(AHB0_INTC + 0x114))
  68. #define INTC_ICCR (*(volatile unsigned long *)(AHB0_INTC + 0x118))
  69. #define INTC_ISCR (*(volatile unsigned long *)(AHB0_INTC + 0x11C))
  70.  
  71. #define INTC_TEST (*(volatile unsigned long *)(AHB0_INTC + 0x124))
  72.  
  73. /* LCD controller */
  74. #define AHB1_LCDC 0x186E8000
  75. #define LCDC_CTRL (*(volatile unsigned long *)(AHB1_LCDC + 0x00))
  76. #define MCU_CTRL (*(volatile unsigned long *)(AHB1_LCDC + 0x04))
  77.  
  78. #define HOR_PERIOD (*(volatile unsigned long *)(AHB1_LCDC + 0x08))
  79. #define VERT_PERIOD (*(volatile unsigned long *)(AHB1_LCDC + 0x0C))
  80. #define HOR_PW (*(volatile unsigned long *)(AHB1_LCDC + 0x10))
  81. #define VERT_PW (*(volatile unsigned long *)(AHB1_LCDC + 0x14))
  82. #define HOR_ACT (*(volatile unsigned long *)(AHB1_LCDC + 0x18))
  83. #define VERT_ACT (*(volatile unsigned long *)(AHB1_LCDC + 0x1C))
  84. #define HOR_BP (*(volatile unsigned long *)(AHB1_LCDC + 0x20))
  85. #define VERT_BP (*(volatile unsigned long *)(AHB1_LCDC + 0x24))
  86. #define LINE0_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x28))
  87.  
  88. #define LINE0_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x2C))
  89. #define LINE1_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x30))
  90. #define LINE1_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x34))
  91. #define LINE2_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x38))
  92. #define LINE2_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x3C))
  93. #define LINE3_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x40))
  94. #define LINE3_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x44))
  95. #define START_X (*(volatile unsigned long *)(AHB1_LCDC + 0x48))
  96. #define START_Y (*(volatile unsigned long *)(AHB1_LCDC + 0x4C))
  97. #define DELTA_X (*(volatile unsigned long *)(AHB1_LCDC + 0x50))
  98. #define DELTA_Y (*(volatile unsigned long *)(AHB1_LCDC + 0x54))
  99. #define LCDC_INTR_MASK (*(volatile unsigned long *)(AHB1_LCDC + 0x58))
  100.  
  101. #define LCDC_STA (*(volatile unsigned long *)(AHB1_LCDC + 0x7C))
  102.  
  103. #define LCD_COMMAND (*(volatile unsigned long *)(AHB1_LCDC + 0x1000))
  104. #define LCD_DATA (*(volatile unsigned long *)(AHB1_LCDC + 0x1004))
  105.  
  106. /* AHB-to-AHB DMA controller */
  107. #define AHB1_DWDMA 0x186F0000
  108. #define DWDMA_SAR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x00 + 0x58*n))
  109. #define DWDMA_DAR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x08 + 0x58*n))
  110. #define DWDMA_LLP(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x10 + 0x58*n))
  111. #define DWDMA_CTL_L(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x18 + 0x58*n))
  112.  
  113. #define DWDMA_CTL_H(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x1C + 0x58*n))
  114. #define DWDMA_SSTAT(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x20 + 0x58*n))
  115. #define DWDMA_DSTAT(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x28 + 0x58*n))
  116. #define DWDMA_SSTATAR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x30 + 0x58*n))
  117. #define DWDMA_DSTATAR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x38 + 0x58*n))
  118. #define DWDMA_CFG_L(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x40 + 0x58*n))
  119. #define DWDMA_CFG_H(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x44 + 0x58*n))
  120.  
  121. #define DWDMA_SGR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x48 + 0x58*n))
  122. #define DWDMA_DSR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x50 + 0x58*n))
  123.  
  124. #define DWDMA_RAW_TFR (*(volatile unsigned long *)(AHB1_DWDMA + 0x2C0))
  125. #define DWDMA_RAW_BLOCK (*(volatile unsigned long *)(AHB1_DWDMA + 0x2C8))
  126. #define DWDMA_RAW_SRCTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x2D0))
  127. #define DWDMA_RAW_DSTTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x2D8))
  128. #define DWDMA_RAW_ERR (*(volatile unsigned long *)(AHB1_DWDMA + 0x2E0))
  129.  
  130. #define DWDMA_STATUS_TFR (*(volatile unsigned long *)(AHB1_DWDMA + 0x2E8))
  131. #define DWDMA_STATUS_BLOCK (*(volatile unsigned long *)(AHB1_DWDMA + 0x2F0))
  132. #define DWDMA_STATUS_SRCTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x2F8))
  133. #define DWDMA_STATUS_DSTTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x300))
  134. #define DWDMA_STATUS_ERR (*(volatile unsigned long *)(AHB1_DWDMA + 0x308))
  135.  
  136. #define DWDMA_MASK_TFR (*(volatile unsigned long *)(AHB1_DWDMA + 0x310))
  137. #define DWDMA_MASK_BLOCK (*(volatile unsigned long *)(AHB1_DWDMA + 0x318))
  138. #define DWDMA_MASK_SRCTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x320))
  139. #define DWDMA_MASK_DSTTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x328))
  140. #define DWDMA_MASK_ERR (*(volatile unsigned long *)(AHB1_DWDMA + 0x330))
  141.  
  142. #define DWDMA_CLEAR_TFR (*(volatile unsigned long *)(AHB1_DWDMA + 0x338))
  143. #define DWDMA_CLEAR_BLOCK (*(volatile unsigned long *)(AHB1_DWDMA + 0x340))
  144. #define DWDMA_CLEAR_SRCTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x348))
  145. #define DWDMA_CLEAR_DSTTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x350))
  146. #define DWDMA_CLEAR_ERR (*(volatile unsigned long *)(AHB1_DWDMA + 0x358))
  147.  
  148. #define DWDMA_STATUS_INT (*(volatile unsigned long *)(AHB1_DWDMA + 0x360))
  149.  
  150. #define DWDMA_REQ_SRC (*(volatile unsigned long *)(AHB1_DWDMA + 0x368))
  151. #define DWDMA_REQ_DST (*(volatile unsigned long *)(AHB1_DWDMA + 0x370))
  152. #define DWDMA_S_REQ_SRC (*(volatile unsigned long *)(AHB1_DWDMA + 0x378))
  153. #define DWDMA_S_REQ_DST (*(volatile unsigned long *)(AHB1_DWDMA + 0x380))
  154. #define DWDMA_L_REQ_SRC (*(volatile unsigned long *)(AHB1_DWDMA + 0x388))
  155. #define DWDMA_L_REQ_DST (*(volatile unsigned long *)(AHB1_DWDMA + 0x390))
  156.  
  157. #define DWDMA_DMA_CFG (*(volatile unsigned long *)(AHB1_DWDMA + 0x398))
  158. #define DWDMA_DMA_CHEN (*(volatile unsigned long *)(AHB1_DWDMA + 0x3A0))
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