/*******************************************************************
*
* Project: DD2 - Assig. 1.2 SAR ADC Ctrl
* Module: sar_adc_ctrl_tb.v
* Description:
> Parametrized in # of bits and # of sampling cycles
> Uses a ring counter (can also use a decoder but that results in more area)
> > 64-128 transistors Vs. 80-160
> State diagram:

            !go                       sample_cyc times
          +----+                  +------+
          |    |                  |      |
        +-+----v--+         +-----+--+   |
        |   IDLE  |         |Sampling|   |
!rst---->         +---go--->+        | <-+
        +----+----+         +----+---+
             ^                   |
             |                   |
          !go|                   |
             |                   v
        +----+----+          +--------+
        | DONE    |          |Conv.   |
        |         +<---------+        +---+
        +-+----+--+          +-----+--+   |
          |    ^                   ^      |#bits times
          |    |                   +------+
          +----+
            go

* Author: Ahmed Ghazy (ax3ghazy@aucegypt.edu)
*
* Changelog:
  > Fri Feb 16 - Done
********************************************************************/
`timescale 1ns/1ns
`default_nettype none


//A simulation of V_REF, V_IN, etc using real (float)
module sar_adc_ctrl_tb;
    parameter resolution = 8;
    parameter sample_cyc = 2;

    //Inputs
    reg clk;
    reg rst_n;
    reg go;
    reg cmp;

    //Outputs
    wire sample;
    wire valid;
    wire [resolution-1:0] result;
    wire [resolution-1:0] value;

    wire [resolution-1:0] result_correct = V_IN/step_size;
    //it can be shown that the output produced can differ from
    //the optimal result by at most 1 (being less by 1)
    wire error = valid && (result_correct-result > 1);

    //Instantiation of Unit Under Test
    sar_adc_ctrl #(.resolution(resolution), .sample_cyc(sample_cyc))
    uut (
        .clk(clk),
        .rst_n(rst_n),
        .go(go),
        .cmp(cmp),
        .sample(sample),
        .valid(valid),
        .result(result),
        .value(value)
    );


    always #5 clk = ~clk;

    real V_REF, V_IN, V_DAC, step_size;
    initial begin
        V_REF = 50.0;
        V_IN = 13.5;
        step_size = V_REF/((1<<resolution)-1);
    end
    always @ *
        V_DAC = value*step_size;
    always @ *
        cmp = V_DAC > V_IN;

    integer i;
    initial begin
    //Inputs initialization
        clk = 0;
        rst_n = 1;
        go = 0;
        cmp = 0;


    //Wait for the reset
        #50;
        @ (negedge clk) rst_n = 0;
        @ (negedge clk) rst_n = 1;
        for (i = 0; i < 128; i = i + 1) begin
            @ (negedge clk) go = 1;
            @ (negedge clk) go = 0;
            #200;
            V_IN = V_REF/((1<<16)-1)*($urandom%(1<<16));
        end




    end

endmodule