CN LAB 4

// online compiler: https://www.tutorialspoint.com/compile_verilog_online.php
// decoder_2x4.v
`timescale 1ns / 1ps

module Decoder(A, B, D);

  input A, B;
  output [3:0] D;
  reg [3:0] D;

  always @ (A or B)
    begin
      if ( A == 0 && B == 0)
        D <= 4'b0001;

      else if ( A == 0 && B == 1)
        D <= 4'b0010;

      else if ( A == 1 && B == 0)
        D <= 4'0100;

      else
        D <= 4'b1000;
    end

endmodule

module Testbench;

  reg A_t, B_t;
  wire [3:0] D_t;

  Decoder Decoder_1(A_t, B_t, D_t);

  initial
    begin

      //case 0
      A_t <= 0; B_t <= 0;
      #1 $display("D_t = %b", D_t);

      //case 1
      A_t <= 0; B_t <= 1;
      #1 $display("D_t = %b", D_t);

      //case 2
      A_t <= 1; B_t <= 0;
      #1 $display("D_t = %b", D_t);

      //case 3
      #1 $display("D_t = %b", D_t);

    end
endmodule

//multiplier_4x4.v


`timescale 1ns / 1ps

module Multiplier(A, B, Result);

    input [3:0] A;
    input [3:0] B;
    output [7:0] Result;
    reg [7:0] Result;

    always @ (A or B)
    begin
        Result <= A * B;
    end

    endmodule

module Testbench;

    reg [3:0] A_t;
    reg [3:0] B_t;
    wire [7:0] Result_t;

    Multiplier Multiplier_1(A_t, B_t, Result_t);

    initial
    begin

        //case 0
        A_t <= 0; B_t <= 0;
        #1 $display("Result_t = %b", Result_t);

        //case 1
        A_t <= 0; B_t <= 4;
        #1 $display("Result_t = %b", Result_t);

        //case 2
        A_t <= 2; B_t <= 4;
        #1 $display("Result_t = %b", Result_t);

        //case 3
        A_t <= 11; B_t <= 3;
        #1 $display("Result_t = %b", Result_t);

    end
endmodule

///half_adder.v

module XOR (A,B,S);
        input A, B;
        output reg S;

        always @ (A or B)
        begin
            S=A^B;
        end
endmodule

module AND(A, B, S);
        input A, B;
        output reg S;

        always @(A or B)
        begin
            S=A&B;
        end
endmodule

module half_adder;

    reg A,B;
    output S, C;

    XOR myXOR(A, B, S);
    AND myAND(A, B, C);

    initial
    begin
        A = 0;
        B = 0;
        #1 $display ("S=%b, C=%b\n",S,C);

        A = 0;
        B = 1;
        #1 $display ("S=%b, C=%b\n", S,C);

        A = 1;
        B = 0;
        #1 $display ("S=%b, C=%b\n", S,C);

        A = 1;
        B = 1;
        #1 $display("S=%b, C=%b\n", S,C);
        end
endmodule

//full_adder_nand_gates.v

module NANDgate(A,B,C);

input A;
input B;
output C;
reg C;

always @ (A or B)
begin
    C~(A & B);
end

endmodule

module testbench;

reg A_t, B_t, C_in;
output S, C_out;
wire w1,w2,w3,w4,w5,w6,w7;

NANDgate my_nand_1(A_t, B_t, w1);
NANDgate my_nand_2(A_t, w1, w2);
NANDgate my_nand_3(w1, B_t, w3);
NANDgate my_nand_4(w2, w3, w4);
NANDgate my_nand_5(C_in, w4, w5);
NANDgate my_nand_6(C_in, w5, w6);
NANDgate my_nand_7(w5, w4, w7);
NANDgate my_nand_8(w5, w1, C_out);
NANDgate my_nand_9(w6, w7, 5);

initial
begin

A_t = 0;
B_t = 0;
C_in = 0;
#1 $display ("S=%b, C=%b\n",S,C_out);

A_t = 1;
B_t = 0;
C_in = 0;
#1 $display("S=%b, C=%b\n", S, C_out);

A_t = 1;
B_t = 1;
C_in = 0;
#1 $display("S=%b, C=%b\n", S,C_out);

end

endmodule