ARM lab_7

;            Computer Architectures - 02LSEOV 02LSEOQ            ;
; author:       Paolo BERNARDI - Politecnico di Torino           ;
; creation:     11 November 2018                                 ;
; last update:  13 November 2018                                 ;
; functionalities:                                               ;
;       nothing but bringing to the reset handler                ;

; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------

; <h> Stack Configuration
;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>

Stack_Size      EQU     0x00000200

                AREA    STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem       SPACE   Stack_Size
__initial_sp


; <h> Heap Configuration
;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>

Heap_Size       EQU     0x00000200

                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem        SPACE   Heap_Size
__heap_limit


                PRESERVE8
                THUMB


; Vector Table Mapped to Address 0 at Reset

                AREA    RESET, DATA, READONLY
                EXPORT  __Vectors

__Vectors       DCD     __initial_sp              ; Top of Stack
                DCD     Reset_Handler             ; Reset Handler
                DCD     NMI_Handler               ; NMI Handler
                DCD     HardFault_Handler         ; Hard Fault Handler
                DCD     MemManage_Handler         ; MPU Fault Handler
                DCD     BusFault_Handler          ; Bus Fault Handler
                DCD     UsageFault_Handler        ; Usage Fault Handler
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     SVC_Handler               ; SVCall Handler
                DCD     DebugMon_Handler          ; Debug Monitor Handler
                DCD     0                         ; Reserved
                DCD     PendSV_Handler            ; PendSV Handler
                DCD     SysTick_Handler           ; SysTick Handler

                ; External Interrupts
                DCD     WDT_IRQHandler            ; 16: Watchdog Timer
                DCD     TIMER0_IRQHandler         ; 17: Timer0
                DCD     TIMER1_IRQHandler         ; 18: Timer1
                DCD     TIMER2_IRQHandler         ; 19: Timer2
                DCD     TIMER3_IRQHandler         ; 20: Timer3
                DCD     UART0_IRQHandler          ; 21: UART0
                DCD     UART1_IRQHandler          ; 22: UART1
                DCD     UART2_IRQHandler          ; 23: UART2
                DCD     UART3_IRQHandler          ; 24: UART3
                DCD     PWM1_IRQHandler           ; 25: PWM1
                DCD     I2C0_IRQHandler           ; 26: I2C0
                DCD     I2C1_IRQHandler           ; 27: I2C1
                DCD     I2C2_IRQHandler           ; 28: I2C2
                DCD     SPI_IRQHandler            ; 29: SPI
                DCD     SSP0_IRQHandler           ; 30: SSP0
                DCD     SSP1_IRQHandler           ; 31: SSP1
                DCD     PLL0_IRQHandler           ; 32: PLL0 Lock (Main PLL)
                DCD     RTC_IRQHandler            ; 33: Real Time Clock
                DCD     EINT0_IRQHandler          ; 34: External Interrupt 0
                DCD     EINT1_IRQHandler          ; 35: External Interrupt 1
                DCD     EINT2_IRQHandler          ; 36: External Interrupt 2
                DCD     EINT3_IRQHandler          ; 37: External Interrupt 3
                DCD     ADC_IRQHandler            ; 38: A/D Converter
                DCD     BOD_IRQHandler            ; 39: Brown-Out Detect
                DCD     USB_IRQHandler            ; 40: USB
                DCD     CAN_IRQHandler            ; 41: CAN
                DCD     DMA_IRQHandler            ; 42: General Purpose DMA
                DCD     I2S_IRQHandler            ; 43: I2S
                DCD     ENET_IRQHandler           ; 44: Ethernet
                DCD     RIT_IRQHandler            ; 45: Repetitive Interrupt Timer
                DCD     MCPWM_IRQHandler          ; 46: Motor Control PWM
                DCD     QEI_IRQHandler            ; 47: Quadrature Encoder Interface
                DCD     PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
                DCD     USBActivity_IRQHandler    ; 49: USB Activity interrupt to wakeup
                DCD     CANActivity_IRQHandler    ; 50: CAN Activity interrupt to wakeup


                IF      :LNOT::DEF:NO_CRP
                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key         DCD     0xFFFFFFFF
                ENDIF


                AREA    |.text|, CODE, READONLY


; Reset Handler

Reset_Handler   PROC
                EXPORT  Reset_Handler             [WEAK]
                LDR     R0, =Reset_Handler

            ; your code here
list_mem    RN  0
i           RN  1
cod         RN  2
prices      RN  3
list_pool   RN  4

            LDR     list_mem,   =list_Price-8                   ;begin the writing of the memory using the values contained in the literal pool
            LDR     list_pool,  =Price_list-8

mem         LDRD    cod, prices,    [list_pool,#8]!             ;Price_list[i]->data
            STRD    cod, prices,    [list_mem,#8]!              ;data->list_Price[i] (we write the mem with the content of R2)
            ADD     i,  #1
            CMP     i,  #28
            BNE     mem
            LDR     list_mem, =list_Price

            ; Selection Sort

l           EQU 0
r           EQU 27

j           RN  2
min         RN  3
temp        RN  4
cod_j       RN  5
cod_min     RN  6
price_min   RN  7
cod_temp    RN  8
price_temp  RN  9
list_i      RN  10
list_min    RN  11

            MOV     i,#l
for_1       CMP     i,#r                            ;for(i=l;i<r;i++)
            BHS     __main                          ;'if i>=r go to __main'
            MOV     min,i
            MOV     j,i
            ADD     j,j,#1                          ;'j=j+1'

for_2       CMP     j,#r                            ;for(j=i+1;j<=r;j++)
            ADDHI   i,i,#1                          ;'if j>r exit for_2 and i++'
            BHI     for_1
            LSL     j,j,#3                          ;'multiply by 8 (2^3) to access the right portion of the mem'
            LSL     min,min,#3
            LDR     cod_j,[list_mem,j]              ;cod[j] (only needed to compare with cod[min], price[j] useless)
            ADD     list_min,list_mem,min           ;'calculate address of data[min], necessary because STRD/LDRD cannot allow to use a register as offset'
            LDRD    cod_min,price_min, [list_min]   ;data[min]  (is both cod[min] and price[min])
            LSR     j,j,#3                          ;'return to right value of j dividing by 8'
            LSR     min,min,#3
            CMP     cod_j,cod_min                   ;if(cod[j]<cod[min])
            MOVLO   min,j                           ;min=j
            LSL     i,i,#3
            LSL     min,min,#3
            ADD     list_i,list_mem,i
            ADD     list_min,list_mem,min
            LDRD    cod_min,price_min, [list_min]
            LDRD    cod_temp,price_temp,[list_i]    ;temp=data[i]
            STRD    cod_min, price_min, [list_i]    ;data[i]=data[min]
            MOV     min,i                           ;'swap index too'
            STRD    cod_temp, price_temp,[list_min] ;data[min]=temp
            LSR     i,i,#3
            LSR     min,min,#3
            ADD     j,j,#1                           ;'j++'
            B       for_2


__main

middle      RN 0
item_add    RN 1
list_add    RN 2
index       RN 3
first       RN 4
last        RN 5
key         RN 6
table       RN 7
price       RN 8
quantity    RN 9
sum         RN 10

            MOV     sum, #0
            LDR     index, Item_num                 ;an LDRB instruction could be used instead of ALIGN in literal pool
            LDR     item_add, =Item_list-8          ;-8 byte needed for retrieving the right data at first cycle
            LDR     list_add, =list_Price

loop        LDR     key,[item_add,#8]!              ;for(i=0;i<4;i++)   key=item[i]

            MOV     first,#0
            MOV     last,#27

while       CMP     last,first                      ;while(last>=first)
            BLO     exit                            ;'if last<first exit'

            ADD     middle,last,first
            LSR     middle,middle,#1                ;middle=first+last/2
            LSL     middle,middle,#3                ;'middle*8 (*4 to move from item, *2 to skip the price) to access to the right address in Price_list'
            LDR     table, [list_add,middle]        ;'table[middle]'
            CMP     table,key                       ;if(key==table[middle])

            ADDEQ   middle,middle,#4                ;'calculate the address of the price in Price_list'
            LDREQ   price,[list_add,middle]
            LDREQ   quantity,[item_add,#4]
            MLAEQ   sum,price,quantity,sum          ;sum+=price*quantity
            BEQ     exit                            ;break

            CMPNE   last,first                      ;if(table!=key && last=first) sum=0 return 0
            MOVEQ   sum,#0
            BEQ     InfLoop

            LSR     middle,middle,#3                ;'calculate the original value of middle not taking count of mul for addresses'
            CMP     key,table
            SUBLO   last,middle,#1                  ;if(key<table[middle]) last=middle-1
            ADDHS   first,middle,#1                 ;else first=middle+1

            B       while
exit
            SUBS    index,index,#1
            BNE     loop

InfLoop         B   InfLoop
            ALIGN
Price_list  DCD 0x010, 228, 0x012, 7,     0x007, 1210, 0x00A, 245
            DCD 0x004, 120, 0x006, 315,   0x016, 722,  0x017, 1217
            DCD 0x04A, 265,  0x01A, 2222, 0x01B, 34,   0x01E, 11
            DCD 0x022, 223,  0x023, 1249, 0x025, 240,  0x027, 112
            DCD 0x02C, 2245, 0x02D, 410,  0x031, 840,  0x033, 945
            DCD 0x036, 3211, 0x039, 112,  0x03C, 719,  0x03E, 661
            DCD 0x042, 230,  0x045, 1112, 0x047, 2627, 0x018, 138


Item_list   DCD 0x022, 14, 0x006, 431, 0x03E, 1210, 0x017, 56342
Item_num    DCB 4
            ALIGN 4                                 ;insert 4 byte of padding to align data
                ENDP


; Dummy Exception Handlers (infinite loops which can be modified)

NMI_Handler     PROC
                EXPORT  NMI_Handler               [WEAK]
                B       .
                ENDP
HardFault_Handler\
                PROC
                EXPORT  HardFault_Handler         [WEAK]
                B       .
                ENDP
MemManage_Handler\
                PROC
                EXPORT  MemManage_Handler         [WEAK]
                B       .
                ENDP
BusFault_Handler\
                PROC
                EXPORT  BusFault_Handler          [WEAK]
                B       .
                ENDP
UsageFault_Handler\
                PROC
                EXPORT  UsageFault_Handler        [WEAK]
                B       .
                ENDP
SVC_Handler     PROC
                EXPORT  SVC_Handler               [WEAK]
                B       .
                ENDP
DebugMon_Handler\
                PROC
                EXPORT  DebugMon_Handler          [WEAK]
                B       .
                ENDP
PendSV_Handler  PROC
                EXPORT  PendSV_Handler            [WEAK]
                B       .
                ENDP
SysTick_Handler PROC
                EXPORT  SysTick_Handler           [WEAK]
                B       .
                ENDP

Default_Handler PROC

                EXPORT  WDT_IRQHandler            [WEAK]
                EXPORT  TIMER0_IRQHandler         [WEAK]
                EXPORT  TIMER1_IRQHandler         [WEAK]
                EXPORT  TIMER2_IRQHandler         [WEAK]
                EXPORT  TIMER3_IRQHandler         [WEAK]
                EXPORT  UART0_IRQHandler          [WEAK]
                EXPORT  UART1_IRQHandler          [WEAK]
                EXPORT  UART2_IRQHandler          [WEAK]
                EXPORT  UART3_IRQHandler          [WEAK]
                EXPORT  PWM1_IRQHandler           [WEAK]
                EXPORT  I2C0_IRQHandler           [WEAK]
                EXPORT  I2C1_IRQHandler           [WEAK]
                EXPORT  I2C2_IRQHandler           [WEAK]
                EXPORT  SPI_IRQHandler            [WEAK]
                EXPORT  SSP0_IRQHandler           [WEAK]
                EXPORT  SSP1_IRQHandler           [WEAK]
                EXPORT  PLL0_IRQHandler           [WEAK]
                EXPORT  RTC_IRQHandler            [WEAK]
                EXPORT  EINT0_IRQHandler          [WEAK]
                EXPORT  EINT1_IRQHandler          [WEAK]
                EXPORT  EINT2_IRQHandler          [WEAK]
                EXPORT  EINT3_IRQHandler          [WEAK]
                EXPORT  ADC_IRQHandler            [WEAK]
                EXPORT  BOD_IRQHandler            [WEAK]
                EXPORT  USB_IRQHandler            [WEAK]
                EXPORT  CAN_IRQHandler            [WEAK]
                EXPORT  DMA_IRQHandler            [WEAK]
                EXPORT  I2S_IRQHandler            [WEAK]
                EXPORT  ENET_IRQHandler           [WEAK]
                EXPORT  RIT_IRQHandler            [WEAK]
                EXPORT  MCPWM_IRQHandler          [WEAK]
                EXPORT  QEI_IRQHandler            [WEAK]
                EXPORT  PLL1_IRQHandler           [WEAK]
                EXPORT  USBActivity_IRQHandler    [WEAK]
                EXPORT  CANActivity_IRQHandler    [WEAK]

WDT_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
PWM1_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
SPI_IRQHandler
SSP0_IRQHandler
SSP1_IRQHandler
PLL0_IRQHandler
RTC_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
ADC_IRQHandler
BOD_IRQHandler
USB_IRQHandler
CAN_IRQHandler
DMA_IRQHandler
I2S_IRQHandler
ENET_IRQHandler
RIT_IRQHandler
MCPWM_IRQHandler
QEI_IRQHandler
PLL1_IRQHandler
USBActivity_IRQHandler
CANActivity_IRQHandler

                B       .

                ENDP


                ALIGN


; User Initial Stack & Heap

                EXPORT  __initial_sp
                EXPORT  __heap_base
                EXPORT  __heap_limit

                AREA DataArea,DATA,READWRITE,ALIGN=3
list_Price      SPACE   28*4*2

                END