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  1. // system_bus.v - wrapper for wishbone master and system bus IP cores
  2. // 03-21-19 E. Brombaugh
  3.  
  4. `default_nettype none
  5.  
  6. module system_bus(
  7. input clk, // system clock
  8. input rst, // system reset
  9. input cs, // chip select
  10. input we, // write enable
  11. input [7:0] addr, // register select
  12. input [7:0] din, // data bus input
  13. output reg [7:0] dout, // data bus output
  14. output rdy, // low-true processor stall
  15. output irq, // high-true interrupt request
  16. inout spi0_mosi, // spi core 0 mosi
  17. inout spi0_miso, // spi core 0 miso
  18. inout spi0_sclk, // spi core 0 sclk
  19. inout spi0_cs0 // spi core 0 cs
  20. );
  21.  
  22. // the wishbone master
  23. wire sbstbi, sbrwi, sbacko;
  24. wire [7:0] sbadri, sbdato, sbdati;
  25. wishbone uwish(
  26. .clk(clk),
  27. .rst(rst),
  28. .cs(cs),
  29. .we(we),
  30. .addr(addr),
  31. .din(din),
  32. .dout(dout),
  33. .rdy(rdy),
  34. .wb_stbo(sbstbi),
  35. .wb_adro(sbadri),
  36. .wb_rwo(sbrwi),
  37. .wb_dato(sbdati),
  38. .wb_acki(sbacko),
  39. .wb_dati(sbdato)
  40. );
  41.  
  42. // temporary
  43. assign irq = 1'b0;
  44.  
  45. // SPI IP Core
  46. wire moe_0, mo_0, si_0; // MOSI components
  47. wire soe_0, mi_0, so_0; // MISO components
  48. wire sckoe_0, scko_0, scki_0; // SCLK components
  49. wire mcsnoe_00, mcsno_00, scsni_0; // CS0 components
  50. SB_SPI #(
  51. .BUS_ADDR74("0b0000")
  52. )
  53. spiInst0 (
  54. .SBCLKI(clk),
  55. .SBRWI(sbrwi),
  56. .SBSTBI(sbstbi),
  57. .SBADRI7(sbadri[7]),
  58. .SBADRI6(sbadri[6]),
  59. .SBADRI5(sbadri[5]),
  60. .SBADRI4(sbadri[4]),
  61. .SBADRI3(sbadri[3]),
  62. .SBADRI2(sbadri[2]),
  63. .SBADRI1(sbadri[1]),
  64. .SBADRI0(sbadri[0]),
  65. .SBDATI7(sbdati[7]),
  66. .SBDATI6(sbdati[6]),
  67. .SBDATI5(sbdati[5]),
  68. .SBDATI4(sbdati[4]),
  69. .SBDATI3(sbdati[3]),
  70. .SBDATI2(sbdati[2]),
  71. .SBDATI1(sbdati[1]),
  72. .SBDATI0(sbdati[0]),
  73. .MI(mi_0),
  74. .SI(si_0),
  75. .SCKI(scki_0),
  76. .SCSNI(scsni_0),
  77. .SBDATO7(sbdato[7]),
  78. .SBDATO6(sbdato[6]),
  79. .SBDATO5(sbdato[5]),
  80. .SBDATO4(sbdato[4]),
  81. .SBDATO3(sbdato[3]),
  82. .SBDATO2(sbdato[2]),
  83. .SBDATO1(sbdato[1]),
  84. .SBDATO0(sbdato[0]),
  85. .SBACKO(sbacko),
  86. .SPIIRQ(),
  87. .SPIWKUP(),
  88. .SO(so_0),
  89. .SOE(soe_0),
  90. .MO(mo_0),
  91. .MOE(moe_0),
  92. .SCKO(scko_0),
  93. .SCKOE(sckoe_0),
  94. .MCSNO3(),
  95. .MCSNO2(),
  96. .MCSNO1(),
  97. .MCSNO0(mcsno_00),
  98. .MCSNOE3(),
  99. .MCSNOE2(),
  100. .MCSNOE1(),
  101. .MCSNOE0(mcsnoe_00)
  102. );
  103.  
  104. // I/O drivers are tri-state output w/ simple input
  105. // MOSI driver
  106. SB_IO #(
  107. .PIN_TYPE(6'b101001),
  108. .PULLUP(1'b0),
  109. .NEG_TRIGGER(1'b0),
  110. .IO_STANDARD("SB_LVCMOS")
  111. ) umosi (
  112. .PACKAGE_PIN(spi0_mosi),
  113. .LATCH_INPUT_VALUE(1'b0),
  114. .CLOCK_ENABLE(1'b0),
  115. .INPUT_CLK(1'b0),
  116. .OUTPUT_CLK(1'b0),
  117. .OUTPUT_ENABLE(moe_0),
  118. .D_OUT_0(mo_0),
  119. .D_OUT_1(1'b0),
  120. .D_IN_0(si_0),
  121. .D_IN_1()
  122. );
  123.  
  124. // MISO driver
  125. SB_IO #(
  126. .PIN_TYPE(6'b101001),
  127. .PULLUP(1'b0),
  128. .NEG_TRIGGER(1'b0),
  129. .IO_STANDARD("SB_LVCMOS")
  130. ) umiso (
  131. .PACKAGE_PIN(spi0_miso),
  132. .LATCH_INPUT_VALUE(1'b0),
  133. .CLOCK_ENABLE(1'b0),
  134. .INPUT_CLK(1'b0),
  135. .OUTPUT_CLK(1'b0),
  136. .OUTPUT_ENABLE(soe_0),
  137. .D_OUT_0(so_0),
  138. .D_OUT_1(1'b0),
  139. .D_IN_0(mi_0),
  140. .D_IN_1()
  141. );
  142.  
  143. // SCK driver
  144. SB_IO #(
  145. .PIN_TYPE(6'b101001),
  146. .PULLUP(1'b0),
  147. .NEG_TRIGGER(1'b0),
  148. .IO_STANDARD("SB_LVCMOS")
  149. ) usclk (
  150. .PACKAGE_PIN(spi0_sclk),
  151. .LATCH_INPUT_VALUE(1'b0),
  152. .CLOCK_ENABLE(1'b0),
  153. .INPUT_CLK(1'b0),
  154. .OUTPUT_CLK(1'b0),
  155. .OUTPUT_ENABLE(sckoe_0),
  156. .D_OUT_0(scko_0),
  157. .D_OUT_1(1'b0),
  158. .D_IN_0(scki_0),
  159. .D_IN_1()
  160. );
  161.  
  162. // CS0 driver
  163. SB_IO #(
  164. .PIN_TYPE(6'b101001),
  165. .PULLUP(1'b0),
  166. .NEG_TRIGGER(1'b0),
  167. .IO_STANDARD("SB_LVCMOS")
  168. ) ucs0 (
  169. .PACKAGE_PIN(spi0_cs0),
  170. .LATCH_INPUT_VALUE(1'b0),
  171. .CLOCK_ENABLE(1'b0),
  172. .INPUT_CLK(1'b0),
  173. .OUTPUT_CLK(1'b0),
  174. .OUTPUT_ENABLE(mcsnoe_00),
  175. .D_OUT_0(mcsno_00),
  176. .D_OUT_1(1'b0),
  177. .D_IN_0(scsni_0),
  178. .D_IN_1()
  179. );
  180.  
  181. endmodule
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